{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T18:51:57Z","timestamp":1725475917018},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,3]]},"DOI":"10.1109\/isqed.2009.4810361","type":"proceedings-article","created":{"date-parts":[[2009,4,3]],"date-time":"2009-04-03T14:50:11Z","timestamp":1238770211000},"page":"594-600","source":"Crossref","is-referenced-by-count":1,"title":["Place and route considerations for voltage interpolated designs"],"prefix":"10.1109","author":[{"given":"Kevin","family":"Brownell","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali Durlov","family":"Khan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Brooks","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gu-Yeon","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466531"},{"key":"11","doi-asserted-by":"crossref","first-page":"495","DOI":"10.1145\/277044.277180","article-title":"MTCMOS hierarchical sizing based on mutual exclusive discharge patterns","author":"kao","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597182"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2005.251687"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1109\/ISQED.2007.66","article-title":"dyanmic power management by combination of dual static supply voltages","author":"agarwal","year":"2007","journal-title":"International Symposium on Quality Electronic Design"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224083"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e88-c.4.509"},{"year":"0","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681626"},{"key":"5","article-title":"a process-variationtolerant floating-point unit with voltage interpolation and variable latency","author":"liang","year":"2008","journal-title":"International Solid-State Circuits Conference"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/92.645070"},{"journal-title":"Cadence SoC Encounter","year":"0","key":"9"},{"year":"0","key":"8","article-title":"opensparc t1 chip design"}],"event":{"name":"2009 10th International Symposium on Quality of Electronic Design (ISQED)","start":{"date-parts":[[2009,3,16]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2009,3,18]]}},"container-title":["2009 10th International Symposium on Quality of Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4804412\/4810250\/04810361.pdf?arnumber=4810361","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T14:34:30Z","timestamp":1497796470000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4810361\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/isqed.2009.4810361","relation":{},"subject":[],"published":{"date-parts":[[2009,3]]}}}