{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:15:57Z","timestamp":1730276157650,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/isqed.2010.5450412","type":"proceedings-article","created":{"date-parts":[[2010,4,20]],"date-time":"2010-04-20T13:45:07Z","timestamp":1271771107000},"page":"163-170","source":"Crossref","is-referenced-by-count":3,"title":["Statistical static timing analysis flow for transistor level macros in a microprocessor"],"prefix":"10.1109","author":[{"given":"Vivek S","family":"Nandakumar","sequence":"first","affiliation":[]},{"given":"David","family":"Newmark","sequence":"additional","affiliation":[]},{"given":"Yaping","family":"Zhan","sequence":"additional","affiliation":[]},{"given":"Malgorzata","family":"Marek-Sadowska","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"2008","journal-title":"Synopsys Version B-2008 06","key":"ref10"},{"key":"ref11","article-title":"A tutorial on principal component analysis","author":"shlens","year":"2009","journal-title":"Salk Institute for Biological Studies"},{"key":"ref12","article-title":"A hierarchical transistor and gate level statistical timing analysis flow for microprocessor designs","author":"sinha","year":"2009","journal-title":"Proc Design Automation Conference session 4u 3s"},{"year":"2005","author":"srivastava","article-title":"Statistical Analysis and Optimization Techniques in Nanometer-ERA VLSI Design","key":"ref13"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/TSM.2008.2011666"},{"year":"0","key":"ref15"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/ISQED.2008.4479726"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TCAD.2005.850834"},{"key":"ref6","article-title":"A methodology for transistor level static timing analysis of a 12 cache on a high performance microprocessor","author":"newmark","year":"2006","journal-title":"Austin Conference on Integrated Systems & Circuits"},{"key":"ref5","first-page":"672","article-title":"Process variation dimension reduction based on SVD","volume":"4","author":"li","year":"2003","journal-title":"Proc of the International Symposium on Circuits and Systems"},{"year":"2007","author":"orshansky","article-title":"Design for manufacturability and statistical design: A constructive approach","key":"ref8"},{"key":"ref7","first-page":"516","article-title":"Statistical timing analysis technology","volume":"43","author":"nitta","year":"2007","journal-title":"Fujitsu Sc Tech J"},{"key":"ref2","article-title":"Variation aware analysis using Primetime-VX","author":"arvind","year":"2009","journal-title":"Proc of Synopsys User Group"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1145\/1065579.1065751"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ICMTS.1990.161743"}],"event":{"name":"2010 11th International Symposium on Quality of Electronic Design (ISQED)","start":{"date-parts":[[2010,3,22]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2010,3,24]]}},"container-title":["2010 11th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5443864\/5450389\/05450412.pdf?arnumber=5450412","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T20:01:27Z","timestamp":1489867287000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5450412\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/isqed.2010.5450412","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}