{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,23]],"date-time":"2025-09-23T12:57:04Z","timestamp":1758632224819},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/isqed.2010.5450415","type":"proceedings-article","created":{"date-parts":[[2010,4,20]],"date-time":"2010-04-20T13:45:07Z","timestamp":1271771107000},"page":"171-175","source":"Crossref","is-referenced-by-count":11,"title":["A framework for logic-aware layout analysis"],"prefix":"10.1109","author":[{"given":"Patrick","family":"Gibson","sequence":"first","affiliation":[]},{"family":"Ziyang Lu","sequence":"additional","affiliation":[]},{"given":"Fedor","family":"Pikus","sequence":"additional","affiliation":[]},{"given":"Sridhar","family":"Srinivasan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","article-title":"Towards Manufacturability Closure: Process Variations and Layout Design","author":"torres","year":"2005","journal-title":"EDP 2005 Workshop"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"359","DOI":"10.1145\/1065579.1065676","article-title":"Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions","author":"yang","year":"2005","journal-title":"Design Automation Conference 2005 Proceedings 42nd"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1117\/12.814872"},{"key":"ref5","article-title":"Electrically Driven Optical Proximity Correction","author":"banerjee","year":"2008","journal-title":"Proc SPIE 6925 69251W"},{"key":"ref2","article-title":"From poly line to transistor: building BSIM models for non-rectangular transistors","author":"poppe","year":"0","journal-title":"Proc SPIE 6516 61560P (2006)"},{"key":"ref1","article-title":"Electrical DFM-Focusing on What Matter to Chip Designers","author":"reed","year":"0","journal-title":"Chip Design Extension Media"}],"event":{"name":"2010 11th International Symposium on Quality of Electronic Design (ISQED)","start":{"date-parts":[[2010,3,22]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2010,3,24]]}},"container-title":["2010 11th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5443864\/5450389\/05450415.pdf?arnumber=5450415","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T07:19:36Z","timestamp":1497856776000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5450415\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isqed.2010.5450415","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}