{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:16:02Z","timestamp":1730276162798,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/isqed.2010.5450487","type":"proceedings-article","created":{"date-parts":[[2010,4,20]],"date-time":"2010-04-20T09:45:07Z","timestamp":1271756707000},"page":"804-811","source":"Crossref","is-referenced-by-count":1,"title":["A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures"],"prefix":"10.1109","author":[{"given":"Sanghamitra","family":"Roy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koushik","family":"Chakraborty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.65"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953283"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289846"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ESIME.2008.4525106"},{"key":"ref16","article-title":"Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management","volume":"27","author":"zhu","year":"2008","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090885"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560164"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977306"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870069"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364517"},{"key":"ref7","article-title":"Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors","author":"li","year":"2006","journal-title":"Proc High Performance Comput Architecture"},{"key":"ref2","article-title":"Rethinking Threshold Voltage Assignment in 3D Mulicore Designs","author":"chakraborty","year":"2010","journal-title":"IEEE International Conference on VLSI Design"},{"key":"ref1","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"}],"event":{"name":"2010 11th International Symposium on Quality of Electronic Design (ISQED)","start":{"date-parts":[[2010,3,22]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2010,3,24]]}},"container-title":["2010 11th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5443864\/5450389\/05450487.pdf?arnumber=5450487","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T23:57:36Z","timestamp":1489881456000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5450487\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/isqed.2010.5450487","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}