{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:02:00Z","timestamp":1759147320058},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/isqed.2011.5770696","type":"proceedings-article","created":{"date-parts":[[2011,5,24]],"date-time":"2011-05-24T19:17:26Z","timestamp":1306264646000},"page":"1-6","source":"Crossref","is-referenced-by-count":7,"title":["Reducing impact of degradation on analog circuits by chopper stabilization and autozeroing"],"prefix":"10.1109","author":[{"given":"Shailesh","family":"More","sequence":"first","affiliation":[]},{"given":"Michael","family":"Fulde","sequence":"additional","affiliation":[]},{"given":"Florian","family":"Chouard","sequence":"additional","affiliation":[]},{"given":"Doris","family":"Schmitt-Landsiedel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/IRPS.2009.5173321"},{"year":"2010","author":"relxpert","journal-title":"Users Manuals BSIMPro+\/RelXpert\/UltraSim Cadence Design Systems Inc","key":"ref11"},{"key":"ref12","article-title":"Sensitivity analysis based analytical evaluation of aging degradation in linear circuits","author":"more","year":"2010","journal-title":"European Solid-State Circuits Conference Fringe Session ESSCIRC"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/TSM.2008.2004329"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/TDMR.2009.2019762"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TED.2005.859570"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/ISSCC.1981.1156191"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ESSCIRC.2010.5619730"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/IRPS.2010.5488724"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/5.542410"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/IRPS.2009.5173224"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/IEDM.2007.4419069"},{"key":"ref9","first-page":"88","article-title":"A cost effective 32nm high-k metal gate cmos technology for low power applications with single-metal gate-first process","author":"chen","year":"2008","journal-title":"Symposium on VLSI Technology"}],"event":{"name":"2011 International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2011,3,14]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2011,3,16]]}},"container-title":["2011 12th International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5764309\/5770683\/05770696.pdf?arnumber=5770696","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T07:30:22Z","timestamp":1490081422000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5770696\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/isqed.2011.5770696","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}