{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:45:36Z","timestamp":1759146336036},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/isqed.2011.5770702","type":"proceedings-article","created":{"date-parts":[[2011,5,24]],"date-time":"2011-05-24T15:17:26Z","timestamp":1306250246000},"page":"1-6","source":"Crossref","is-referenced-by-count":15,"title":["3DICE: 3D IC cost evaluation based on fast tier number estimation"],"prefix":"10.1109","author":[{"given":"Cheng-Chi","family":"Chan","sequence":"first","affiliation":[]},{"given":"Yen-Ting","family":"Yu","sequence":"additional","affiliation":[]},{"given":"Iris Hui-Ru","family":"Jiang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/SOCCON.2009.5398032"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796507"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref13","first-page":"175","article-title":"A linear time heuristic for improving network partitions","author":"fiduccia","year":"0","journal-title":"Proc DAC"},{"key":"ref14","article-title":"TSV-Aware 3D Physical Design Tool Needs for Faster Mainstream Acceptance of 3D ICs","author":"lim","year":"2010","journal-title":"DAC Knowledge Center Article"},{"key":"ref15","article-title":"Multilevel k-way hypergraph partitioning","author":"karypis","year":"1998","journal-title":"Technical Report TR 98–036 CS Dept"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751864"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/92.902258"},{"year":"0","key":"ref18"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397268"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796486"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.150"},{"key":"ref8","article-title":"Large scale circuit partitioning with loose\/stable net removal and signal flow based hierarchical clustering","author":"cong","year":"1997","journal-title":"Technical Report 970005"},{"key":"ref7","first-page":"483","article-title":"A multilevel multilayer partitioning algorithm for three dimensional integrated circuits","author":"hu","year":"2010","journal-title":"Proc ISQED"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"journal-title":"International Technology Roadmap for Semiconductors (ITRS)","year":"0","key":"ref1"},{"key":"ref9","article-title":"A study of through-silicon-via impact on the 3D stacked IC layout","author":"kin","year":"2009","journal-title":"Proc ICCAD"}],"event":{"name":"2011 International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2011,3,14]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2011,3,16]]}},"container-title":["2011 12th International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5764309\/5770683\/05770702.pdf?arnumber=5770702","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T03:38:12Z","timestamp":1490067492000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5770702\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/isqed.2011.5770702","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}