{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T17:05:11Z","timestamp":1725555911695},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/isqed.2011.5770708","type":"proceedings-article","created":{"date-parts":[[2011,5,24]],"date-time":"2011-05-24T19:17:26Z","timestamp":1306264646000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers"],"prefix":"10.1109","author":[{"given":"Michael","family":"Wieckowski","sequence":"first","affiliation":[]},{"given":"Gregory K.","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Daeyeon","family":"Kim","sequence":"additional","affiliation":[]},{"given":"David","family":"Blaauw","sequence":"additional","affiliation":[]},{"given":"Dennis","family":"Sylvester","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917568"},{"key":"ref3","first-page":"46","article-title":"A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme","author":"kushida","year":"2008","journal-title":"Proceedings of IEEE Symposium on VLSI Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456943"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907173"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810057"},{"key":"ref1","first-page":"382","article-title":"A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit- $\\beta$ ratio Memory Cell","author":"kawasumi","year":"2008","journal-title":"proceedings of the IEEE International Solid State Circuits Conference"}],"event":{"name":"2011 International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2011,3,14]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2011,3,16]]}},"container-title":["2011 12th International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5764309\/5770683\/05770708.pdf?arnumber=5770708","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T07:42:42Z","timestamp":1490082162000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5770708\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isqed.2011.5770708","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}