{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:16:26Z","timestamp":1730276186279,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/isqed.2011.5770786","type":"proceedings-article","created":{"date-parts":[[2011,5,24]],"date-time":"2011-05-24T15:17:26Z","timestamp":1306250246000},"page":"1-6","source":"Crossref","is-referenced-by-count":6,"title":["Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory"],"prefix":"10.1109","author":[{"given":"Kyungsu","family":"Kang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jongpil","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sungjoo","family":"Yoo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chong-Min","family":"Kyung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"1479","article-title":"Three-dimensional chip-multiprocessor runtime thermal management","volume":"27","author":"zhu","year":"2008","journal-title":"IEEE TCAD"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373610"},{"journal-title":"CACTI 4 0","year":"2006","author":"tarjan","key":"ref12"},{"journal-title":"International technology roadmap for semiconductors Technical report","year":"2005","key":"ref13"},{"key":"ref14","first-page":"1042","article-title":"Temperature and supply voltage aware performance and power modeling at microarchitecture level","volume":"24","author":"liao","year":"2005","journal-title":"IEEE TCAD"},{"journal-title":"Intel core2 duo processors and Intel core2 extreme processors for platforms based on mobile Intel 965 express chipset family ” Datasheet","year":"2008","key":"ref15"},{"key":"ref16","first-page":"501","article-title":"HotSpot: A compact thermal modeling method for CMOS VLSI systems","volume":"14","author":"huang","year":"2006","journal-title":"IEEE TVLSI"},{"journal-title":"Standard Performance Evaluation Corporation","year":"0","key":"ref17"},{"journal-title":"Free Computational Fluid Dynamics","year":"0","key":"ref18"},{"key":"ref19","first-page":"444","article-title":"Design space exploration for 3-D cache","volume":"16","author":"tsai","year":"2008","journal-title":"IEEE TVLSI"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/40.641597"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2059290"},{"journal-title":"Tezzaron datasheets","year":"0","key":"ref5"},{"key":"ref8","first-page":"34","article-title":"The ALPBench benchmark suite for complex multimedia applications","author":"li","year":"2005","journal-title":"Proc Int Symp Workload Characterization"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref2","first-page":"98","article-title":"An 80-tile 1.28 TFLOPS networks-on-chip in 65nm CMOS","author":"vangal","year":"0","journal-title":"Proc ISSCC"},{"journal-title":"Intel Products","year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.105"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2501626.2512457"},{"key":"ref21","first-page":"390","article-title":"Optimal topoloty exploration for application-specific 3D architectures","author":"ozturk","year":"0","journal-title":"Proc ASPDAC"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594306"}],"event":{"name":"2011 International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2011,3,14]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2011,3,16]]}},"container-title":["2011 12th International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5764309\/5770683\/05770786.pdf?arnumber=5770786","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T02:43:59Z","timestamp":1490064239000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5770786\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/isqed.2011.5770786","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}