{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T18:25:36Z","timestamp":1725474336112},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/isqed.2011.5770816","type":"proceedings-article","created":{"date-parts":[[2011,5,24]],"date-time":"2011-05-24T15:17:26Z","timestamp":1306250246000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["Constructive AIG optimization considering input weights"],"prefix":"10.1109","author":[{"given":"Thiago","family":"Figueiro","sequence":"first","affiliation":[]},{"given":"Renato Perez","family":"Ribas","sequence":"additional","affiliation":[]},{"given":"Andre Inacio","family":"Reis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref12","first-page":"143","article-title":"Factor cuts","author":"chatterjee","year":"0","journal-title":"ICCAD '06"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456946"},{"key":"ref14","first-page":"168","article-title":"High-Quality Circuit Synthesis for Modem Technologies","author":"jozwiak","year":"2008","journal-title":"ISQED"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647772"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675028"},{"key":"ref4","first-page":"532","article-title":"DAG-aware AIG rewriting a fresh look at combinational logic synthesis","author":"mishchenko","year":"0","journal-title":"DAC '06"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"0","key":"ref3"},{"key":"ref6","first-page":"195","author":"golumbic","year":"0","journal-title":"Factoring Logic Functions Using Graph Partitioning"},{"key":"ref5","first-page":"149","article-title":"Large-scale SOP minimization using decomposition and functional properties","author":"mishchenko","year":"0","journal-title":"DAC '03"},{"key":"ref8","article-title":"FRAIGs: A Unifying Representation for Logic Synthesis and Verification","author":"mishchenko","year":"2005","journal-title":"ERL Technical Report EECS Dept"},{"journal-title":"No more counting of Literals Presentation of discussion Group 3 at IWLS","year":"2003","key":"ref7"},{"key":"ref2","article-title":"SIS: A system for sequential circuit synthesis","author":"sentovich","year":"1992","journal-title":"Tech Rep UCB\/ERL M92\/41"},{"journal-title":"Logic Synthesis and Verification Algorithms","year":"1996","author":"hachtel","key":"ref1"},{"key":"ref9","article-title":"Constructive AIG Optimization through Functional Composition","author":"figueiro","year":"2011","journal-title":"1st ERDIAP Workshop Exploiting Regularity in the Design of IPs Architectures and Platforms"}],"event":{"name":"2011 International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2011,3,14]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2011,3,16]]}},"container-title":["2011 12th International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5764309\/5770683\/05770816.pdf?arnumber=5770816","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T01:55:27Z","timestamp":1490061327000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5770816\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/isqed.2011.5770816","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}