{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:07:30Z","timestamp":1725491250560},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/isqed.2012.6187469","type":"proceedings-article","created":{"date-parts":[[2012,4,25]],"date-time":"2012-04-25T16:08:50Z","timestamp":1335370130000},"page":"21-26","source":"Crossref","is-referenced-by-count":2,"title":["TSV and DFT cost aware circuit partitioning for 3D-SOCs"],"prefix":"10.1109","author":[{"given":"Amit","family":"Kumar","sequence":"first","affiliation":[]},{"given":"Sudhakar M.","family":"Reddy","sequence":"additional","affiliation":[]},{"given":"Irith","family":"Pomeranz","sequence":"additional","affiliation":[]},{"given":"Bernd","family":"Becker","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.80"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1543438.1543442"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469556"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783750"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457087"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751450"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647651"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2051732"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271086"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2011.52"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763229"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2009.48"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763230"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"5","first-page":"483","article-title":"A multilevel multilayer partitioning algorithm for three dimensional integrated circuits","author":"hu","year":"2010","journal-title":"ISQED"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770751"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.125"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.115"}],"event":{"name":"2012 13th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2012,3,19]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2012,3,21]]}},"container-title":["Thirteenth International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6182938\/6187454\/06187469.pdf?arnumber=6187469","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T10:24:00Z","timestamp":1490091840000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6187469\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/isqed.2012.6187469","relation":{},"subject":[],"published":{"date-parts":[[2012,3]]}}}