{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T06:35:34Z","timestamp":1723012534596},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/isqed.2012.6187499","type":"proceedings-article","created":{"date-parts":[[2012,4,25]],"date-time":"2012-04-25T16:08:50Z","timestamp":1335370130000},"source":"Crossref","is-referenced-by-count":7,"title":["Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects"],"prefix":"10.1109","author":[{"given":"Young-Joon","family":"Lee","sequence":"first","affiliation":[]},{"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","first-page":"609","article-title":"Complexity Analysis and Speedup Techniques for Optimal Buffer Insertion with Minimum Cost","author":"shi","year":"2004","journal-title":"Proc Asia and South Pacific Design Automation Conf"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112223"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1989.77002"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/43.331409"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.823343"},{"key":"12","year":"0","journal-title":"Nangate 45nm open cell library"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855889"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781363"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1997.597214"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006095"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825861"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1063\/1.1697872"},{"key":"5","first-page":"1735","article-title":"Buffer Planning for 3D ICs","author":"dong","year":"2009","journal-title":"Proc IEEE Int Symp on Circuits and Systems"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1985.22046"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/4.494206"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2034508"}],"event":{"name":"2012 13th International Symposium on Quality Electronic Design (ISQED)","location":"Santa Clara, CA, USA","start":{"date-parts":[[2012,3,19]]},"end":{"date-parts":[[2012,3,21]]}},"container-title":["Thirteenth International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6182938\/6187454\/06187499.pdf?arnumber=6187499","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T11:55:54Z","timestamp":1490097354000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6187499\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/isqed.2012.6187499","relation":{},"subject":[],"published":{"date-parts":[[2012,3]]}}}