{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T18:16:09Z","timestamp":1725387369948},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/isqed.2012.6187549","type":"proceedings-article","created":{"date-parts":[[2012,4,25]],"date-time":"2012-04-25T16:08:50Z","timestamp":1335370130000},"page":"561-565","source":"Crossref","is-referenced-by-count":3,"title":["An accurate current source model for CMOS based combinational logic cell"],"prefix":"10.1109","author":[{"given":"Baljit","family":"Kaur","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandeep","family":"Vundavalli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S. K.","family":"Manhas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Dasgupta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bulusu","family":"Anand","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"HSPICE The Gold Standard for Accurate Circuit Simulation","year":"2009","key":"17"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2024945"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382562"},{"key":"16","first-page":"363","article-title":"Waveform independent gate models for accurate timing analysis","author":"li","year":"2005","journal-title":"Proc ICCD"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.835136"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219030"},{"journal-title":"Composite Current Source","article-title":"CCS timing white paper","year":"2005","key":"11"},{"journal-title":"Cadence Technical Paper","article-title":"Delay calculation meets the nanometer era","year":"2005","key":"12"},{"key":"3","first-page":"652","article-title":"Worst-case circuit delay taking into account power supply variations","author":"kouroussis","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.808448"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484737"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.802274"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1998.666509"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.808448"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159686"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/43.506141"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167535"},{"key":"8","article-title":"Evaluating the factors influencing timing accuracy","author":"dartu","year":"0","journal-title":"Proc of TAU Feb 2005"}],"event":{"name":"2012 13th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2012,3,19]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2012,3,21]]}},"container-title":["Thirteenth International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6182938\/6187454\/06187549.pdf?arnumber=6187549","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T10:05:25Z","timestamp":1490090725000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6187549\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/isqed.2012.6187549","relation":{},"subject":[],"published":{"date-parts":[[2012,3]]}}}