{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T08:23:55Z","timestamp":1725783835437},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/isqed.2012.6187553","type":"proceedings-article","created":{"date-parts":[[2012,4,25]],"date-time":"2012-04-25T16:08:50Z","timestamp":1335370130000},"page":"586-591","source":"Crossref","is-referenced-by-count":4,"title":["24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V&lt;inf&gt;DDmin&lt;\/inf&gt; limited ultra low voltage logic circuits"],"prefix":"10.1109","author":[{"given":"Tadashi","family":"Yasufuku","sequence":"first","affiliation":[]},{"given":"Koji","family":"Hirairi","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Pu","sequence":"additional","affiliation":[]},{"given":"Yun Fei","family":"Zheng","sequence":"additional","affiliation":[]},{"given":"Ryo","family":"Takahashi","sequence":"additional","affiliation":[]},{"given":"Masato","family":"Sasaki","sequence":"additional","affiliation":[]},{"given":"Hiroshi","family":"Fuketa","sequence":"additional","affiliation":[]},{"given":"Atsushi","family":"Muramatsu","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Nomura","sequence":"additional","affiliation":[]},{"given":"Hirofumi","family":"Shinohara","sequence":"additional","affiliation":[]},{"given":"Makoto","family":"Takamiya","sequence":"additional","affiliation":[]},{"given":"Takayasu","family":"Sakurai","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E93.C.332"},{"key":"2","first-page":"342","article-title":"A 0.27V 30MHz 17.7nJ\/transform 1024-pt complex FFT core with super-pipelining","author":"seok","year":"2011","journal-title":"International Solid-State Circuits Conference (ISSCC)"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746345"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2011.6044897"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2159285"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024942"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993598"}],"event":{"name":"2012 13th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2012,3,19]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2012,3,21]]}},"container-title":["Thirteenth International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6182938\/6187454\/06187553.pdf?arnumber=6187553","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T10:28:51Z","timestamp":1490092131000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6187553\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/isqed.2012.6187553","relation":{},"subject":[],"published":{"date-parts":[[2012,3]]}}}