{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:53:07Z","timestamp":1747806787008},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/isqed.2012.6187563","type":"proceedings-article","created":{"date-parts":[[2012,4,25]],"date-time":"2012-04-25T20:08:50Z","timestamp":1335384530000},"page":"663-671","source":"Crossref","is-referenced-by-count":4,"title":["Theory of redundancy for logic circuits to maximize yield\/area"],"prefix":"10.1109","author":[{"given":"Mohammad","family":"Mirza-Aghatabar","sequence":"first","affiliation":[]},{"given":"Melvin A.","family":"Breuer","sequence":"additional","affiliation":[]},{"given":"Sandeep K.","family":"Gupta","sequence":"additional","affiliation":[]},{"given":"Shahin","family":"Nazarian","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.1997.630748"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/66.311339"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1147\/rd.276.0549"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/5.775417"},{"key":"16","first-page":"21","article-title":"SRAM yield estimation in the early stage of the design cycle","author":"kim","year":"1997","journal-title":"Proc Memory Technology Design and Testing Proceedings International Workshop"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511816321"},{"key":"14","doi-asserted-by":"crossref","first-page":"640","DOI":"10.1109\/DATE.2000.840853","article-title":"Reducing the complexity of defect level modeling using the clustering effect","author":"de sousa","year":"2000","journal-title":"Proc IEEE Design Automation and Test in Europe"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.51"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1988.207790"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ISMSS.1989.77246"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/16.2435"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/12.338099"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240944"},{"key":"24","doi-asserted-by":"crossref","first-page":"160","DOI":"10.1145\/1080695.1069984","article-title":"Rescue: A microarchitecture for testability and defect tolerance","author":"schuchman","year":"2005","journal-title":"Proc 25th Int l Symp Computer Architecture"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675498"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1991.199948"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/ARRAYS.1988.18100"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1991.146709"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1147\/rd.435.0863"},{"year":"0","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2003.1230947"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456998"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976918"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454124"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2009.40"},{"journal-title":"Intel Technology Journal","year":"2011","key":"6"},{"key":"5","article-title":"Systematic mechanisms limited yield (SMLY) study","author":"leachman","year":"2003","journal-title":"Int'l SEMATECH"},{"year":"0","key":"31"},{"year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/CITISIA.2009.5224225"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1983.12619"}],"event":{"name":"2012 13th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2012,3,19]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2012,3,21]]}},"container-title":["Thirteenth International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6182938\/6187454\/06187563.pdf?arnumber=6187563","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,27]],"date-time":"2019-06-27T23:07:20Z","timestamp":1561676840000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6187563\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/isqed.2012.6187563","relation":{},"subject":[],"published":{"date-parts":[[2012,3]]}}}