{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T21:59:59Z","timestamp":1729634399864,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,3]]},"DOI":"10.1109\/isqed.2013.6523656","type":"proceedings-article","created":{"date-parts":[[2013,6,13]],"date-time":"2013-06-13T16:54:03Z","timestamp":1371142443000},"page":"487-493","source":"Crossref","is-referenced-by-count":1,"title":["Tabu search based cells placement in nanofabric architectures with restricted connectivity"],"prefix":"10.1109","author":[{"given":"S. M.","family":"Sait","sequence":"first","affiliation":[]},{"given":"A. M.","family":"Arafeh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Iterative Computer Algorithms with Applications in Engineering Solving Combinatorial Optimization Problems","year":"1999","author":"sait","key":"13"},{"key":"14","doi-asserted-by":"crossref","first-page":"1929","DOI":"10.1109\/ISCAS.1989.100747","article-title":"Combinational profiles of sequential benchmark circuits","volume":"3","author":"brglez","year":"1989","journal-title":"Circuits and Systems 1989 IEEE International Symposium on"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2010.22"},{"key":"12","first-page":"1","article-title":"An integrated optimization approach for nano-hybrid circuit cell mapping","author":"xia","year":"2011","journal-title":"Nanotechnology IEEE Transactions on"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/18\/3\/035204"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/16\/6\/045"},{"key":"1","first-page":"433","author":"butts","year":"2002","journal-title":"Molecular Electronics Devices Systems and Tools for Gigagate Gigabit Chips"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603746"},{"key":"7","first-page":"213","article-title":"CMOL FPGA circuits","author":"strukov","year":"2006","journal-title":"Proc of Int Conf on Computer Design CDES2006"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/16\/1\/028"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1166\/sam.2011.1177"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117221"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2008.923261"},{"key":"8","first-page":"75","article-title":"Routing congestion removing of CMOL FPGA circuits by a recursive method","author":"hamidipour","year":"2010","journal-title":"Proceedings of the 9th WSEAS International Conference on Microelectronics Nanoelectronics Optoelectronics MINO'10"}],"event":{"name":"2013 14th International Symposium on Quality Electronic Design (ISQED 2013)","start":{"date-parts":[[2013,3,4]]},"location":"Santa Clara, CA","end":{"date-parts":[[2013,3,6]]}},"container-title":["International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6520923\/6523572\/06523656.pdf?arnumber=6523656","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T10:35:46Z","timestamp":1498041346000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6523656\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/isqed.2013.6523656","relation":{},"subject":[],"published":{"date-parts":[[2013,3]]}}}