{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,8]],"date-time":"2025-09-08T06:31:26Z","timestamp":1757313086871,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,3]]},"DOI":"10.1109\/isqed.2013.6523658","type":"proceedings-article","created":{"date-parts":[[2013,6,13]],"date-time":"2013-06-13T20:54:03Z","timestamp":1371156843000},"page":"502-507","source":"Crossref","is-referenced-by-count":7,"title":["Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation"],"prefix":"10.1109","author":[{"given":"Y.","family":"Hara-Azumi","sequence":"first","affiliation":[]},{"given":"H.","family":"Tomiyama","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"15"},{"key":"13","first-page":"7","article-title":"A scheduling algorithm in highlevel synthesis for soft error tolerance with chained operations","volume":"107 dc 17","author":"imamura","year":"2007","journal-title":"IEICE technical report"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.15"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.99"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/HASE.2008.46"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2010.04.003"},{"key":"2","first-page":"18","article-title":"Reliability analysis of memories protected with bics and a per-word parity bit","volume":"15","author":"revirieo","year":"2010","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2008.4695897"},{"key":"10","first-page":"409","article-title":"Reliability-aware system synthesis","author":"ab","year":"2007","journal-title":"Proceedings of Design Automation and Test"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/12.869319"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.258"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028924"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.68"},{"key":"9","first-page":"1124","article-title":"SEU-aware resource binding for modular redundancy based designs on FP GAs","author":"golshan","year":"2009","journal-title":"Proceedings of Design Automation and Test"},{"key":"8","doi-asserted-by":"crossref","first-page":"1476","DOI":"10.1109\/TCAD.2004.835132","article-title":"Fault seeure datapath synthesis using hybrid time and hardware redundancy","volume":"23","author":"kaijie","year":"2004","journal-title":"IEEE Trans Computer Aided Design of Circuits and Systems"}],"event":{"name":"2013 14th International Symposium on Quality Electronic Design (ISQED 2013)","start":{"date-parts":[[2013,3,4]]},"location":"Santa Clara, CA","end":{"date-parts":[[2013,3,6]]}},"container-title":["International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6520923\/6523572\/06523658.pdf?arnumber=6523658","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T14:35:45Z","timestamp":1498055745000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6523658\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/isqed.2013.6523658","relation":{},"subject":[],"published":{"date-parts":[[2013,3]]}}}