{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T07:59:30Z","timestamp":1729670370295,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,3]]},"DOI":"10.1109\/isqed.2013.6523660","type":"proceedings-article","created":{"date-parts":[[2013,6,13]],"date-time":"2013-06-13T16:54:03Z","timestamp":1371142443000},"page":"516-523","source":"Crossref","is-referenced-by-count":2,"title":["Efficient translation validation of high-level synthesis"],"prefix":"10.1109","author":[{"family":"Tun Li","sequence":"first","affiliation":[]},{"family":"Yang Guo","sequence":"additional","affiliation":[]},{"family":"Wanwei Liu","sequence":"additional","affiliation":[]},{"family":"Chiyuan Ma","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"crossref","first-page":"19","DOI":"10.1090\/psapm\/019\/0235771","article-title":"Assigning meaning to programs","author":"floyd","year":"1967","journal-title":"Proc 19th Symp Appl"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1145\/363235.363259"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1109\/ISSS.1995.520630"},{"year":"0","key":"16"},{"key":"13","first-page":"223","article-title":"VOC: A methodology for the translation validation of optimizing compilers","volume":"9","author":"zuck","year":"2003","journal-title":"J Univ Comput Sci"},{"year":"2008","author":"moura","journal-title":"Z3 An efficient SMT solver","key":"14"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/TCAD.2010.2042889"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/ICVD.2003.1183177"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/DATE.1999.761097"},{"key":"2","first-page":"294","article-title":"Formal synthesis in circuit design-A classification and survey","author":"kumar","year":"1996","journal-title":"Proc FMCAD"},{"year":"1992","author":"gajski","journal-title":"High-Level Synthesis Introduction to Chip and System Design","key":"1"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/TCAD.2009.2035542"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/TCAD.2007.913390"},{"year":"2004","author":"kim","journal-title":"Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (Fsmd)","key":"6"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1016\/j.jss.2006.12.547"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1023\/A:1011250531814"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/ICCAD.1998.144317"},{"key":"8","first-page":"497","article-title":"Equivalence checking of scheduling with speculative code transformations in high-level synthesis","author":"lee","year":"2010","journal-title":"Proc of ASPDAC 2010"}],"event":{"name":"2013 14th International Symposium on Quality Electronic Design (ISQED 2013)","start":{"date-parts":[[2013,3,4]]},"location":"Santa Clara, CA","end":{"date-parts":[[2013,3,6]]}},"container-title":["International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6520923\/6523572\/06523660.pdf?arnumber=6523660","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T10:35:45Z","timestamp":1498041345000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6523660\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/isqed.2013.6523660","relation":{},"subject":[],"published":{"date-parts":[[2013,3]]}}}