{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:04:57Z","timestamp":1761581097964,"version":"3.28.0"},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,3]]},"DOI":"10.1109\/isqed.2013.6523679","type":"proceedings-article","created":{"date-parts":[[2013,6,13]],"date-time":"2013-06-13T16:54:03Z","timestamp":1371142443000},"page":"651-657","source":"Crossref","is-referenced-by-count":5,"title":["CMOS inverter delay model based on DC transfer curve for slow input"],"prefix":"10.1109","author":[{"given":"F. S.","family":"Marranghello","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A. I.","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R. P.","family":"Ribas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"19","DOI":"10.1109\/TCSII.2009.2024245"},{"doi-asserted-by":"publisher","key":"35","DOI":"10.1109\/ICECS.2011.6122371"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/4.400428"},{"doi-asserted-by":"publisher","key":"36","DOI":"10.1145\/1228784.1228857"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1049\/ip-cds:20041016"},{"doi-asserted-by":"publisher","key":"33","DOI":"10.1109\/TED.2006.884077"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1109\/43.310902"},{"key":"34","first-page":"5","article-title":"Tree-based transistor topology extraction algorithm for library-free logic synthesis","author":"xue","year":"2004","journal-title":"Semiconductor Electronics 2004 ICSE 2004 IEEE International Conference on"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/82.877142"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/4.5953"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/4.736655"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/ISCAS.2009.5118433"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/JSSC.1986.1052525"},{"doi-asserted-by":"publisher","key":"21","DOI":"10.1063\/1.1697872"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1109\/TCAD.2009.2035539"},{"doi-asserted-by":"publisher","key":"22","DOI":"10.1109\/ISCAS.1996.542014"},{"key":"23","doi-asserted-by":"crossref","first-page":"1027","DOI":"10.1109\/43.35557","article-title":"An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation","volume":"8","author":"jun","year":"1989","journal-title":"Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on"},{"doi-asserted-by":"publisher","key":"24","DOI":"10.1109\/4.68126"},{"doi-asserted-by":"publisher","key":"25","DOI":"10.1109\/43.317470"},{"doi-asserted-by":"publisher","key":"26","DOI":"10.1109\/43.759070"},{"doi-asserted-by":"publisher","key":"27","DOI":"10.1109\/TCSII.2005.851992"},{"doi-asserted-by":"publisher","key":"28","DOI":"10.1109\/43.992767"},{"year":"2010","author":"weste","journal-title":"CMOS VLSI Design","key":"29"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/4.293109"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/TCAD.1987.1270271"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/TCSI.2004.830692"},{"key":"1","first-page":"627","article-title":"Switching response of complementary symmetry MOS transistor logic circuits","volume":"25","author":"burns","year":"1964","journal-title":"RCA Rev"},{"doi-asserted-by":"publisher","key":"30","DOI":"10.1109\/4.346"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/VLSI.Design.2009.48"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/16.75219"},{"doi-asserted-by":"publisher","key":"32","DOI":"10.1016\/j.mejo.2005.09.020"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/4.52187"},{"doi-asserted-by":"publisher","key":"31","DOI":"10.1109\/4.792617"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/4.658636"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/81.662699"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/4.604081"}],"event":{"name":"2013 14th International Symposium on Quality Electronic Design (ISQED 2013)","start":{"date-parts":[[2013,3,4]]},"location":"Santa Clara, CA","end":{"date-parts":[[2013,3,6]]}},"container-title":["International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6520923\/6523572\/06523679.pdf?arnumber=6523679","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T10:35:48Z","timestamp":1498041348000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6523679\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/isqed.2013.6523679","relation":{},"subject":[],"published":{"date-parts":[[2013,3]]}}}