{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T11:48:24Z","timestamp":1763466504038,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/isqed.2014.6783300","type":"proceedings-article","created":{"date-parts":[[2014,4,16]],"date-time":"2014-04-16T21:24:16Z","timestamp":1397683456000},"page":"9-15","source":"Crossref","is-referenced-by-count":1,"title":["Exploiting static and dynamic locality of timing errors in robust L1 cache design"],"prefix":"10.1109","author":[{"given":"Hu","family":"Chen","sequence":"first","affiliation":[]},{"given":"Sanghamitra","family":"Roy","sequence":"additional","affiliation":[]},{"given":"Koushik","family":"Chakraborty","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.13"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2011","author":"patterson","key":"17"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742777"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/1070838.1070856"},{"key":"15","first-page":"15","article-title":"Yield-Aware cache architectures","author":"ozdemir","year":"2006","journal-title":"Proc of MICRO"},{"key":"16","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1145\/1629911.1629929","article-title":"selective wordline voltage boosting for caches to manage yield under process variations","author":"yan pan","year":"2009","journal-title":"2009 46th ACM\/IEEE Design Automation Conference dac"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.2"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.30"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.19"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1995.476815"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"2","article-title":"Exploring high bandwidth pipelined cache architecture for scaled technology","author":"amit agarwal","year":"2003","journal-title":"DATE"},{"key":"1","doi-asserted-by":"crossref","first-page":"1804","DOI":"10.1109\/JSSC.2005.852159","article-title":"Process variation in embedded memories: Failure analysis and variation aware architecture","volume":"40","author":"agarwal","year":"2005","journal-title":"IEEE J Solid-State Circuits"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123011"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"6","first-page":"366","volume":"15","author":"gregg","year":"2007","journal-title":"Post Silicon Power\/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000067"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.028"},{"key":"8","article-title":"The microarchitecture of the pentium 4 processor","author":"hinton","year":"2001","journal-title":"Intel Technology Journal"}],"event":{"name":"2014 15th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2014,3,3]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2014,3,5]]}},"container-title":["Fifteenth International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6779216\/6783285\/06783300.pdf?arnumber=6783300","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T11:43:28Z","timestamp":1498131808000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6783300\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/isqed.2014.6783300","relation":{},"subject":[],"published":{"date-parts":[[2014,3]]}}}