{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:43:03Z","timestamp":1761648183540,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/isqed.2014.6783323","type":"proceedings-article","created":{"date-parts":[[2014,4,16]],"date-time":"2014-04-16T17:24:16Z","timestamp":1397669056000},"page":"184-188","source":"Crossref","is-referenced-by-count":5,"title":["Comparative analysis of clock distribution networks for TSV-based 3D IC designs"],"prefix":"10.1109","author":[{"given":"Mir Mohammad","family":"Navidi","sequence":"first","affiliation":[]},{"given":"Gyung-Su","family":"Byun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228572"},{"key":"17","first-page":"184","article-title":"Pre-bond testable low-power clock tree design for 3D stacked ICs","author":"xin","year":"2009","journal-title":"Dig Tech Papers ICCAD"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS.2011.6100195"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.808433"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705326"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2101890"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2252211"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/4.663576"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938067"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2099590"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"journal-title":"Piscataway Clock Distribution Networks in VLSI Circuits and Systems","year":"1995","author":"friedman","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2073724"},{"key":"7","doi-asserted-by":"crossref","first-page":"715","DOI":"10.1109\/43.924825","article-title":"Gated clock routing for lowpower microprocessor design","volume":"20","author":"oh","year":"2001","journal-title":"IEEE Trans on Computer-Aided Design"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/81.841927"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/224081.224083"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/4.726547"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2098130"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419900"}],"event":{"name":"2014 15th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2014,3,3]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2014,3,5]]}},"container-title":["Fifteenth International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6779216\/6783285\/06783323.pdf?arnumber=6783323","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T07:43:29Z","timestamp":1498117409000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6783323\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/isqed.2014.6783323","relation":{},"subject":[],"published":{"date-parts":[[2014,3]]}}}