{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,27]],"date-time":"2025-11-27T06:33:34Z","timestamp":1764225214194},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/isqed.2014.6783324","type":"proceedings-article","created":{"date-parts":[[2014,4,16]],"date-time":"2014-04-16T17:24:16Z","timestamp":1397669056000},"page":"189-196","source":"Crossref","is-referenced-by-count":11,"title":["Delay and power optimization with TSV-aware 3D floorplanning"],"prefix":"10.1109","author":[{"given":"Mohammad A.","family":"Ahmed","sequence":"first","affiliation":[]},{"given":"Malgorzata","family":"Chrzanowska-Jeske","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/FTFC.2013.6577778"},{"key":"16","article-title":"Tsv capacitance aware 3d floorplanning","author":"ahmed","year":"2013","journal-title":"3D System Integration Conference (3D-IC"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1572471.1572486"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1811100.1811108"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2050012"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2190537"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2101910"},{"journal-title":"ITRS","year":"0","key":"2"},{"key":"1","first-page":"214","author":"borkar","year":"2011","journal-title":"3d Integration for Energy Efficient System Design"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2174640"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1983.21093"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306542"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026200"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2008.4479795"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2055247"},{"key":"8","article-title":"Empirical models for wiring capacitances in vlsi","author":"wu","year":"1996","journal-title":"Proc IEEE Int Sym on Circuits and Systems"}],"event":{"name":"2014 15th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2014,3,3]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2014,3,5]]}},"container-title":["Fifteenth International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6779216\/6783285\/06783324.pdf?arnumber=6783324","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T12:43:26Z","timestamp":1490273006000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6783324\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/isqed.2014.6783324","relation":{},"subject":[],"published":{"date-parts":[[2014,3]]}}}