{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T18:25:44Z","timestamp":1725560744420},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/isqed.2014.6783394","type":"proceedings-article","created":{"date-parts":[[2014,4,16]],"date-time":"2014-04-16T21:24:16Z","timestamp":1397683456000},"page":"692-699","source":"Crossref","is-referenced-by-count":4,"title":["Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design"],"prefix":"10.1109","author":[{"given":"Matheus T.","family":"Moreira","sequence":"first","affiliation":[]},{"given":"Julian J. H.","family":"Pontes","sequence":"additional","affiliation":[]},{"given":"Ney L. V.","family":"Calazans","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2011.6122210"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187530"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2011.6085103"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2012.29"},{"key":"16","first-page":"11","article-title":"Qdi latches characteristics and asynchronous linear-pipeline performance analysis","author":"yahya","year":"2006","journal-title":"TIMA Technical Report TR 06\/06-03"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.1996.542821"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511674730"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2012.6463637"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2013.6674779"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2003.1199173"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MPOT.2010.935825"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4612-4476-9_35"},{"key":"1","article-title":"Quasi-delay-insensitive circuits are turing-complete","author":"manohar","year":"1996","journal-title":"International Symposium on Advanced Research in Asynchronous Circuits and Systems"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1016\/S0141-9331(03)00092-9"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.61"},{"key":"6","first-page":"2006","author":"sokolov","year":"2006","journal-title":"Automated synthesis of asynchronous circuits using direct mapping for control and data paths"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2012.6344444"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.875789"},{"key":"9","first-page":"126","article-title":"An alternating spacer AES cryptoprocessor","author":"murphy","year":"2006","journal-title":"European Solid-State Circuits Conference"},{"key":"8","first-page":"471","article-title":"Sidechannel attack mitigation using dual-spacer dual-rail delay-insensitive logic (D3L","author":"cilio","year":"2010","journal-title":"Southeastcon"}],"event":{"name":"2014 15th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2014,3,3]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2014,3,5]]}},"container-title":["Fifteenth International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6779216\/6783285\/06783394.pdf?arnumber=6783394","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T16:48:45Z","timestamp":1490287725000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6783394\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/isqed.2014.6783394","relation":{},"subject":[],"published":{"date-parts":[[2014,3]]}}}