{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,6]],"date-time":"2024-08-06T06:36:42Z","timestamp":1722926202928},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/isqed.2015.7085447","type":"proceedings-article","created":{"date-parts":[[2015,4,16]],"date-time":"2015-04-16T15:16:36Z","timestamp":1429197396000},"source":"Crossref","is-referenced-by-count":2,"title":["Enhancing system-wide power integrity in 3D ICs with power gating"],"prefix":"10.1109","author":[{"given":"Hailang","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emre","family":"Salman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000454"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2016614"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024945"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2483028.2483125"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001247"},{"key":"ref15","year":"0","journal-title":"FreePDK45"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364663"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026200"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1109\/ISLPED.2013.6629271","article-title":"Characterizing and evaluating voltage noise in multi-core near-threshold processors","author":"zhang","year":"2013","journal-title":"Proc Int Symp Low-Power Electronics Design"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1002\/0471660302"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2223553"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2007.4387161"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.120"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2167359"},{"key":"ref8","first-page":"559","article-title":"Benefits and Costs of Power-gating Technique","author":"jiang","year":"2005","journal-title":"Proceedings of IEEE International Conference on Computer Design"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6248907"},{"key":"ref2","author":"salman","year":"2012","journal-title":"High Performance Integrated Circuits"},{"key":"ref1","author":"pavlidis","year":"2010","journal-title":"Three-Dimensional Integrated Circuit Design"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2187081"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479040"}],"event":{"name":"2015 16th International Symposium on Quality Electronic Design (ISQED)","location":"Santa Clara, CA, USA","start":{"date-parts":[[2015,3,2]]},"end":{"date-parts":[[2015,3,4]]}},"container-title":["Sixteenth International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7080985\/7085355\/07085447.pdf?arnumber=7085447","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T05:35:50Z","timestamp":1498196150000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7085447\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/isqed.2015.7085447","relation":{},"subject":[],"published":{"date-parts":[[2015,3]]}}}