{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T19:48:37Z","timestamp":1729626517419,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/isqed.2015.7085497","type":"proceedings-article","created":{"date-parts":[[2015,4,16]],"date-time":"2015-04-16T15:16:36Z","timestamp":1429197396000},"page":"610-614","source":"Crossref","is-referenced-by-count":3,"title":["6-T SRAM performance assessment with stacked silicon nanowire MOSFETs"],"prefix":"10.1109","author":[{"given":"Ya-Chi","family":"Huang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meng-Hsueh","family":"Chiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Chou","family":"Hsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shiou-Ying","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2046070"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2139213"},{"journal-title":"International Technology Roadmap for Semiconductors (ITRS 2011)","year":"0","key":"ref12"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"2371","DOI":"10.1109\/TED.2014.2323059","article-title":"Design of gate-all-around silicon MOSFETs for 6-T SRAM area efficiency and yield","volume":"61","author":"liao","year":"2014","journal-title":"IEEE Trans Electron Devices"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346955"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2013.11.002"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.913744"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2007.10.050"},{"key":"ref8","first-page":"1","article-title":"6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs","author":"liao","year":"2013","journal-title":"Proc IEEE VLSI-TSA"},{"key":"ref7","first-page":"448","article-title":"Critical current $(\\text{I}_{\\text{CRIT}})$ based SPICE model extraction for SRAM cell","author":"chen","year":"2008","journal-title":"Proc IEEE ICSICT"},{"key":"ref2","first-page":"2078","article-title":"Improving bulk FinFET DC performance in comparison to SOl FinFET","volume":"86","author":"poljak","year":"2009","journal-title":"Solid-State Electronics"},{"key":"ref1","first-page":"94","article-title":"Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate","author":"li","year":"2009","journal-title":"Proc VLSI Tech Symp"},{"journal-title":"Sentaurus Device User Guide Synopsys Inc ver D-2010 03","year":"2010","key":"ref9"}],"event":{"name":"2015 16th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2015,3,2]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2015,3,4]]}},"container-title":["Sixteenth International Symposium on Quality Electronic Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7080985\/7085355\/07085497.pdf?arnumber=7085497","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T05:35:51Z","timestamp":1498196151000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7085497\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/isqed.2015.7085497","relation":{},"subject":[],"published":{"date-parts":[[2015,3]]}}}