{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,22]],"date-time":"2026-01-22T22:25:55Z","timestamp":1769120755873,"version":"3.49.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,3]]},"DOI":"10.1109\/isqed.2016.7479181","type":"proceedings-article","created":{"date-parts":[[2016,5,26]],"date-time":"2016-05-26T16:27:41Z","timestamp":1464280061000},"page":"88-94","source":"Crossref","is-referenced-by-count":35,"title":["Low power data-aware STT-RAM based hybrid cache architecture"],"prefix":"10.1109","author":[{"given":"Mohsen","family":"Imani","sequence":"first","affiliation":[]},{"given":"Shruti","family":"Patil","sequence":"additional","affiliation":[]},{"given":"Tajana","family":"Rosing","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0454"},{"key":"ref11","first-page":"373","article-title":"MASC: Ultra-Low Energy Multiple-Access Single-Charge TCAM for Approximate Computing","author":"mohsen imani","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742958"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"ref14","article-title":"AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches","author":"mittal","year":"2014","journal-title":"IEEE Computer Architecture Letters"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993611"},{"key":"ref16","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","author":"wu","year":"2009","journal-title":"IEEE DATE"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2015.7180588"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2231020"},{"key":"ref19","article-title":"Back-gate controlled asymmetrical memory cell and memory using the cell","author":"chuang","year":"2007","journal-title":"Google Patents"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2007.912983"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742972"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372637"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2164543"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.224"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISoC.2011.6081626"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155659"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039420"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993623"},{"key":"ref1","first-page":"55","article-title":"SRAM leakage suppression by minimizing standby supply voltage","author":"qin","year":"2004","journal-title":"IEEE ISQED"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2014.984640"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744314"},{"key":"ref21","first-page":"73","article-title":"Processor caches built using multilevel spin-transfer torque ram cells","author":"chen","year":"2011","journal-title":"IEEE ISLPED"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref23","first-page":"52","article-title":"Exploiting narrow-width values for improving non-volatile cache lifetime","author":"duan","year":"2014","journal-title":"IEEE DATE"},{"key":"ref26","first-page":"994","article-title":"Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory","volume":"31","author":"dong","year":"2012","journal-title":"IEEE ICCAD"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset","volume":"33","author":"martin","year":"2005","journal-title":"ACM SIGARCH Computer Architecture News"}],"event":{"name":"2016 17th International Symposium on Quality Electronic Design (ISQED)","location":"Santa Clara, CA, USA","start":{"date-parts":[[2016,3,15]]},"end":{"date-parts":[[2016,3,16]]}},"container-title":["2016 17th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7470728\/7479140\/07479181.pdf?arnumber=7479181","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T11:08:49Z","timestamp":1498302529000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7479181\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/isqed.2016.7479181","relation":{},"subject":[],"published":{"date-parts":[[2016,3]]}}}