{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,15]],"date-time":"2025-11-15T17:07:43Z","timestamp":1763226463879,"version":"3.28.0"},"reference-count":59,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.1109\/isqed.2017.7918287","type":"proceedings-article","created":{"date-parts":[[2017,5,4]],"date-time":"2017-05-04T16:32:38Z","timestamp":1493915558000},"page":"23-28","source":"Crossref","is-referenced-by-count":21,"title":["Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing"],"prefix":"10.1109","author":[{"given":"Wei-Hao","family":"Chen","sequence":"first","affiliation":[]},{"given":"Win-San","family":"Khwa","sequence":"additional","affiliation":[]},{"given":"Jun-Yi","family":"Li","sequence":"additional","affiliation":[]},{"given":"Wei-Yu","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Huan-Ting","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Yongpan","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Wang","sequence":"additional","affiliation":[]},{"family":"Huaqiang Wu","sequence":"additional","affiliation":[]},{"family":"Huazhong Yang","sequence":"additional","affiliation":[]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757392"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487802"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280761"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2013.6691028"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346730"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2253412"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487695"},{"key":"ref36","first-page":"76c","article-title":"RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94 x reduction in restore energy for frequent-off instant-on applications","author":"lee","year":"2015","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2329915"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2192661"},{"key":"ref28","first-page":"26.1.1","article-title":"Fully Functional Perpendicular STT-MRAM Macro Embedded in 40 nm Logic for Energy-efficient IOT Applications","author":"lu","year":"2015","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724551"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838430"},{"key":"ref2","first-page":"38","article-title":"Value creation in SOC\/MCU applications by embedded nonvolatile memory evolutions","author":"hatanaka","year":"2007","journal-title":"IEEE Asian Solid-state Circuits Conf (ASSCC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176866"},{"key":"ref20","first-page":"302","article-title":"A non-volatile look-up table design using PCM (phase-change memory) cells","author":"wen","year":"2011","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582108"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047136"},{"key":"ref24","first-page":"24.1.1","article-title":"Extended scalability of perpendicular STT-MRAM towards sub-20 nm MTJ node","author":"kim","year":"2011","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047131"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479127"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479129"},{"key":"ref50","first-page":"2179","article-title":"Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing","author":"duygu","year":"2011","journal-title":"Nano Lett 12"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/24\/38\/382001"},{"key":"ref59","first-page":"14","article-title":"A spiking neuromorphic design with resistive crossbar","author":"chenchen","year":"2015","journal-title":"Proceedings of the 52nd Annual Design Automation Conference"},{"key":"ref58","first-page":"860","article-title":"Spiking neural network with rram: Can we use it for real-world application?","author":"tianqi","year":"2015","journal-title":"Proceedings of the 2015 Design Automation & Test in Europe Conference & Exhibition EDA Consortium (DATE)"},{"key":"ref57","article-title":"PRIME: A Novel Processing-In-Memory Architecture for Neural Network Computation in ReRAM-based Main Memory","volume":"43","author":"ping","year":"2016","journal-title":"Proceedings of ISCA"},{"key":"ref56","first-page":"13","article-title":"Merging the interface: Power, area and accuracy co-optimization for rram crossbar-based mixed-signal computing system","author":"boxun","year":"2015","journal-title":"Proceedings of the 52nd Annual Design Automation Conference"},{"key":"ref55","first-page":"189","article-title":"Energy efficient RRAM spiking neural network for real time classification","author":"yu","year":"2015","journal-title":"Proceedings of the 25th edition of the great lakes symposium on VLSI"},{"key":"ref54","article-title":"Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture","author":"zhao","year":"2014","journal-title":"International Joint Conference on Neural Networks (IJCNN)"},{"key":"ref53","article-title":"Arbitrary Waveform Generation Using Memristive Cross Bar Array","author":"subhankar","year":"2014","journal-title":"Advances in Computing and Communications (ICACC)"},{"key":"ref52","article-title":"The Effect of Variation on Neuromorphic Network Based on 1T1R Memristor Array","author":"peng","year":"0","journal-title":"2015 15th Non-Volatile Memory Technology Symposium (NVMTS 2015)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2011.6157181"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722184"},{"key":"ref40","first-page":"84","article-title":"4.7 A 65nm ReRAM-enabled nonvolatile processor with 6x reduction in restore time and 4x higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic","author":"liu","year":"2016","journal-title":"ISSCC Digest of Technical Papers of IEEE InternationalSolid-State Circuits Conference"},{"key":"ref12","first-page":"1","article-title":"ReRAM-based 4T2R nonvolatile TCAM with 7 NVM-stress reduction, 4 improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing","author":"huang","year":"2014","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2049867"},{"key":"ref14","first-page":"10.2.1","article-title":"Demonstration of 3D Vertical RRAM with Ultra Low-leakage, High-selectivity and Self-compliance Memory Cells","author":"luo","year":"2015","journal-title":"Tech Dig IEEE Int Electron Devices Meet (IEDM)"},{"key":"ref15","first-page":"10.5.1","article-title":"1Kbit FINFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process","author":"pan","year":"2015","journal-title":"Tech Dig IEEE Int Electron Devices Meet (IEDM)"},{"key":"ref16","first-page":"17.2.1","article-title":"Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications","author":"piccolboni","year":"2015","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref17","first-page":"1","article-title":"Fully CMOS Compatible 3D Vertical RRAM with Self-aligned Self-selective Cell Enabling Sub-5nm Scaling","author":"xu","year":"2016","journal-title":"Symp VLSI Technol Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2016.2614513"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047138"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746342"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2011.5783209"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2426531"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341281"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2014.7021430"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059068"},{"key":"ref49","first-page":"17.6.1","article-title":"High density neuromorphic system with Mo\/Pr0. 7Ca0. 3MnO3 synapse and NbO2 IMT oscillator neuron","author":"kibong","year":"2015","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6164968"},{"key":"ref46","first-page":"29.4.1","article-title":"Capacity optimization of emerging memory systems: A shannon-inspired approach to device characterization","author":"jesse","year":"2014","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref45","first-page":"4.4.1","article-title":"Large-scale neural networks implemented with non-volatile memory as the synaptic weight element: Comparative performance analysis (accuracy, speed, and power)","author":"burr","year":"2015","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref48","first-page":"17.1.1","article-title":"NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with On-chip neuron circuits for continuous in-situ learning","author":"kim","year":"2015","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref47","first-page":"2206","article-title":"Visual pattern extraction using energy-efficient &#x201C;2-PCM synapse&#x201D; neuromorphic architecture","author":"olivier","year":"2012","journal-title":"IEEE Trans Electron Devices 59"},{"key":"ref42","first-page":"17.3.1","article-title":"Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect","author":"shimeng","year":"2015","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724691"},{"key":"ref44","first-page":"4.7.1","article-title":"Oxide based nanoscale analog synapse device for neural signal recognition system","author":"daeseok","year":"2015","journal-title":"IEEE InternationalElectron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref43","first-page":"17.4.1","article-title":"Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt\/A12O3\/TiO2?? x\/Pt Memristors","author":"prezioso","year":"2015","journal-title":"Tech Dig IEEE Int Electron Devices Meeting (IEDM)"}],"event":{"name":"2017 18th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2017,3,14]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2017,3,15]]}},"container-title":["2017 18th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7910185\/7918273\/07918287.pdf?arnumber=7918287","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T15:45:56Z","timestamp":1513179956000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7918287\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":59,"URL":"https:\/\/doi.org\/10.1109\/isqed.2017.7918287","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}