{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:04:33Z","timestamp":1766066673098,"version":"3.28.0"},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.1109\/isqed.2017.7918351","type":"proceedings-article","created":{"date-parts":[[2017,5,4]],"date-time":"2017-05-04T16:32:38Z","timestamp":1493915558000},"page":"413-418","source":"Crossref","is-referenced-by-count":6,"title":["In&Out: Restructuring for threshold logic network optimization"],"prefix":"10.1109","author":[{"given":"Chia-Chun","family":"Lin","sequence":"first","affiliation":[]},{"given":"Chiao-Wei","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Chun-Yao","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Yung-Chih","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1965.264136"},{"journal-title":"Threshold Logic","year":"1962","author":"winder","key":"ref32"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1961.29"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2008.159"},{"year":"0","key":"ref36"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366167"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839468"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"574","DOI":"10.1109\/TNANO.2014.2312177","article-title":"Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic","volume":"13","author":"deliang","year":"2014","journal-title":"IEEE Trans Nanotechnology"},{"key":"ref11","first-page":"145","article-title":"A VLSI-optimal constructive algorithm for classification problems","author":"draghici","year":"1997","journal-title":"International Journal of Smart Engineering System Design"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2008.4585793"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000671"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2100232"},{"key":"ref15","first-page":"222","article-title":"A Non-ILP Based Threshold Logic Synthesis Methodology","author":"gowda","year":"2007","journal-title":"Proc International Workshop on Logic and Synthesis"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483925"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1228784.1228813"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.1971.5218091"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1080\/00207217008900256"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2010.1089"},{"key":"ref4","first-page":"63","article-title":"On Existential and Constructive Neural Complexity Results","author":"beiu","year":"2003","journal-title":"Neural Networks and Computational Intelligence"},{"key":"ref27","first-page":"768","article-title":"Logic Synthesis for Regular Fabric Realized in Quantum dot Cellular Automata","author":"perkowski","year":"2004","journal-title":"J Multiple-Valued Logic Soft Computing"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.816365"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024920"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691123"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1117\/12.497792"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428059"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2422094.2422099"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-7012(00)00201-3"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.362"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20030989"},{"key":"ref20","first-page":"397","article-title":"Pareto-Based Multiobjective Machine Learning: An Overview and Case Studies","author":"jin","year":"2008","journal-title":"IEEE Trans on Systems"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IWV.2001.923145"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105360"},{"journal-title":"Threshold Logic and Its Applications","year":"1971","author":"muroga","key":"ref24"},{"key":"ref23","first-page":"1","article-title":"Rewiring for Threshold Logic Circuit Minimization","author":"lin","year":"2014","journal-title":"Proc DATE"},{"key":"ref26","article-title":"Resonant Tunneling Device Logic Circuit","author":"pacha","year":"1999","journal-title":"DortmundGerhard-Mercator University of Duisburg Germany Tech Rep"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372610"}],"event":{"name":"2017 18th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2017,3,14]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2017,3,15]]}},"container-title":["2017 18th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7910185\/7918273\/07918351.pdf?arnumber=7918351","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T11:59:01Z","timestamp":1498391941000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7918351\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/isqed.2017.7918351","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}