{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:45:46Z","timestamp":1772725546896,"version":"3.50.1"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/isqed.2018.8357260","type":"proceedings-article","created":{"date-parts":[[2018,5,18]],"date-time":"2018-05-18T21:30:27Z","timestamp":1526679027000},"page":"25-30","source":"Crossref","is-referenced-by-count":2,"title":["Hybrid-comp: A criticality-aware compressed last-level cache"],"prefix":"10.1109","author":[{"given":"Amin","family":"Jadidi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohammad","family":"Arjomand","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahmut T.","family":"Kandemir","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2016.79"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2017.56"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830823"},{"key":"ref13","article-title":"Adaptive data compression for high-performance low-power on-chip networks","author":"jin","year":"0","journal-title":"ser MICRO-41"},{"key":"ref14","article-title":"Frequent value compression in packet-based noc architectures","author":"zhou","year":"0","journal-title":"ser ASP-DAC ‘09"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241625"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"377","DOI":"10.1145\/2370816.2370870","article-title":"Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches","author":"gennady pekhimenko","year":"2012","journal-title":"In International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542288"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665696"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360154"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203753"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081426"},{"key":"ref2","article-title":"C-pack: A high-performance microprocessor cache compression algorithm","author":"chen","year":"2010","journal-title":"IEEE Trans VLSI"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1145\/1028176.1006719","article-title":"Adaptive cache compression for highperformance pracessors","author":"alameldeen","year":"2004","journal-title":"SIGARCH Comput Archit News"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485930"}],"event":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","location":"Santa Clara, CA","start":{"date-parts":[[2018,3,13]]},"end":{"date-parts":[[2018,3,14]]}},"container-title":["2018 19th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8354411\/8357243\/08357260.pdf?arnumber=8357260","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,2]],"date-time":"2023-09-02T18:32:03Z","timestamp":1693679523000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8357260\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/isqed.2018.8357260","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}