{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:52:48Z","timestamp":1725396768663},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/isqed.2018.8357297","type":"proceedings-article","created":{"date-parts":[[2018,5,18]],"date-time":"2018-05-18T17:30:27Z","timestamp":1526664627000},"page":"257-261","source":"Crossref","is-referenced-by-count":0,"title":["Verification methodology to guarantee low routing resistance to well taps"],"prefix":"10.1109","author":[{"given":"Mohammed","family":"Fakhruddin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kuok-Khian","family":"Lo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James","family":"Karp","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael J.","family":"Hart","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Min-Hsing P.","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"35","author":"wang","year":"0","journal-title":"On-Chip ESD Protection for Integrated Circuits An IC Design Perspective"},{"key":"ref3","first-page":"323","author":"liu","year":"2001","journal-title":"MOSFET Models for Spice Simulation"},{"journal-title":"Circuits for and methods of providing a charge device model ground path using substrate taps in and integrated circuit device” US Patent # 9 462 674 B1","year":"2016","author":"fakhruddin","key":"ref6"},{"journal-title":"Cell-level electrostatic discharge protection for an integrated circuit","year":"2014","author":"james","key":"ref5"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1201\/b19714-29"},{"key":"ref2","article-title":"FinFET MPSoC 32 Gb\/s Transceivers: Custom ESD Protection and Verification","author":"james","year":"2016","journal-title":"IEEE 59th Int Midwest Symp on Circuits and Systems"},{"key":"ref1","article-title":"Power Distribution Planning","author":"saleh","year":"0","journal-title":"EE Times 4\/17\/2002"}],"event":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2018,3,13]]},"location":"Santa Clara, CA","end":{"date-parts":[[2018,3,14]]}},"container-title":["2018 19th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8354411\/8357243\/08357297.pdf?arnumber=8357297","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,25]],"date-time":"2022-01-25T23:59:14Z","timestamp":1643155154000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8357297\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/isqed.2018.8357297","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}