{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:18:35Z","timestamp":1730276315618,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/isqed.2019.8697425","type":"proceedings-article","created":{"date-parts":[[2019,4,26]],"date-time":"2019-04-26T03:49:36Z","timestamp":1556250576000},"page":"98-103","source":"Crossref","is-referenced-by-count":3,"title":["Simulation Based Assessment of SRAM Data Retention Voltage"],"prefix":"10.1109","author":[{"given":"Z.","family":"Dong","sequence":"first","affiliation":[]},{"given":"X.","family":"Cao","sequence":"additional","affiliation":[]},{"given":"M. Ahosan Ul","family":"Karim","sequence":"additional","affiliation":[]},{"given":"V.","family":"Joshi","sequence":"additional","affiliation":[]},{"given":"T.","family":"Klick","sequence":"additional","affiliation":[]},{"given":"J.","family":"Schmid","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.913744"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146928"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609437"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892153"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.869786"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382534"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339737"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/16.333844"},{"key":"ref18","first-page":"841","article-title":"Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuations","author":"takeuchi","year":"1996","journal-title":"Proceedings of the International Electron Devices Meeting (IEDM)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2010.5551461"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ETW.2002.1029634"},{"key":"ref4","first-page":"55","article-title":"SRAM leakage suppression by minimizing standby supply voltage","author":"qin","year":"2004","journal-title":"Proc of ISQED"},{"key":"ref27","article-title":"A comprehensive study of cobalt salicide-induced SRAM leakage for 90nm CMOST technology","volume":"54","author":"yang","year":"2007","journal-title":"IEEE Trans Elec Dev"},{"key":"ref3","article-title":"Statistical modeling for the minimum standby voltage of a full SRAM array","author":"wang","year":"0","journal-title":"ESSCIRC 2007"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/EEEI.2012.6377025"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2005.1497065"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061810"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775921"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929760"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001941"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"ref1","article-title":"High-performance and lowe-power challenges for sub-70nm microprocessor circuits","author":"krishnamurthy","year":"2002","journal-title":"CICC"},{"journal-title":"Fundamentals of Modern VLSI Devices","year":"1998","author":"taur","key":"ref20"},{"journal-title":"Matching Properties of Deep Sub-Micron MOS Transistors","year":"2005","author":"croon","key":"ref22"},{"journal-title":"MOSFET Modeling and BSIM User Guide","year":"1999","author":"cheng","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2015.7112760"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2015.7112759"},{"key":"ref26","article-title":"A junction leakage mechanism and its effect on advanc SRAM failure","author":"maji","year":"2013","journal-title":"Int Reliability Physics Symp (IRPS)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-1749-1"}],"event":{"name":"2019 20th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2019,3,6]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2019,3,7]]}},"container-title":["20th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682005\/8697223\/08697425.pdf?arnumber=8697425","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:11:52Z","timestamp":1657854712000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8697425\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/isqed.2019.8697425","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}