{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:18:40Z","timestamp":1730276320544,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/isqed.2019.8697596","type":"proceedings-article","created":{"date-parts":[[2019,4,26]],"date-time":"2019-04-26T03:49:36Z","timestamp":1556250576000},"page":"33-38","source":"Crossref","is-referenced-by-count":0,"title":["Fast Mapping-Based High-Level Synthesis of Pipelined Circuits"],"prefix":"10.1109","author":[{"given":"Chaofan","family":"Li","sequence":"first","affiliation":[]},{"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358040"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2209291.2209302"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1455229.1455230"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/512529.512550"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.75629"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147025"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174268"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/73560.73562"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2002.1000291"},{"journal-title":"LLVM Language Reference Manual","year":"0","author":"lattner","key":"ref19"},{"key":"ref4","first-page":"2011","article-title":"Bambu: A free framework for the high level synthesis of complex applications","volume":"29","author":"pilato","year":"2012","journal-title":"DATE University Booth"},{"journal-title":"Xilinx Vivado High-level Synthesis","year":"0","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CODESISSS.2015.7331371"},{"key":"ref5","article-title":"Spark: A high-level synthesis framework for applying parallelizing compiler transformations;","author":"gupta","year":"2003","journal-title":"VLSI Design"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488795"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8_8"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref9","first-page":"456","article-title":"De-sign space exploration of multiple loops on FPGAs using high level synthesis;","author":"zhong","year":"2014","journal-title":"ICCD"},{"key":"ref1","article-title":"A reconfigurable fabric for accelerating large-scale datacenter services","author":"putnam","year":"2014","journal-title":"ISCA"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/115372.115320"},{"journal-title":"LegUp documentation 4 0","year":"2015","key":"ref22"},{"key":"ref21","first-page":"6","article-title":"Saving costs with the SRL16E","author":"chapman","year":"2008","journal-title":"XILINX TechXclusives"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1468075.1468121"},{"key":"ref23","article-title":"Parallel prefix sum (scan) with CUDA","author":"harris","year":"2007","journal-title":"GPU Gems"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339272"}],"event":{"name":"2019 20th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2019,3,6]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2019,3,7]]}},"container-title":["20th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682005\/8697223\/08697596.pdf?arnumber=8697596","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:12:30Z","timestamp":1657854750000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8697596\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/isqed.2019.8697596","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}