{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,21]],"date-time":"2025-04-21T22:07:45Z","timestamp":1745273265482,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/isqed.2019.8697625","type":"proceedings-article","created":{"date-parts":[[2019,4,26]],"date-time":"2019-04-26T03:49:36Z","timestamp":1556250576000},"page":"241-246","source":"Crossref","is-referenced-by-count":5,"title":["Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET"],"prefix":"10.1109","author":[{"given":"Hung-Han","family":"Lin","sequence":"first","affiliation":[]},{"given":"Vita Pi-Ho","family":"Hu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"405","DOI":"10.1021\/nl071804g","article-title":"Use of negative capacitance to provide voltage amplification for low power nanoscale devices","volume":"8","author":"salahuddin","year":"2008","journal-title":"Nano Lett"},{"key":"ref3","article-title":"Demonstration of p-type In0. 7Ga0. 3As\/GaAs0. 35Sb0. 65 and n-type GaAs0. 4Sb0. 6\/In0. 65Ga0. 35As complimentary heterojunction vertical Tunnel FETs for ultra-low power logic","author":"pandey","year":"2015","journal-title":"Symp on VLSI Tech"},{"journal-title":"Sentaurus TCAD N-2017-9 Manual","year":"0","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268443"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2604860"},{"key":"ref5","first-page":"39","article-title":"0. 2V Adiabatic NC-FinFET with 0. 6 mA\/um Ion and 0. 1 nA\/um Ioff","author":"hu","year":"2015","journal-title":"Device Research Conference (DRC)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.899389"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2017.2658688"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.57.04FD02"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573444"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724561"},{"key":"ref1","first-page":"14","article-title":"Green Transistor-A VDD Scaling Path for Future Low Power ICs","author":"hu","year":"2008","journal-title":"VLSI-TSA"}],"event":{"name":"2019 20th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2019,3,6]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2019,3,7]]}},"container-title":["20th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682005\/8697223\/08697625.pdf?arnumber=8697625","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:12:30Z","timestamp":1657854750000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8697625\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/isqed.2019.8697625","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}