{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:18:41Z","timestamp":1730276321439,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/isqed.2019.8697701","type":"proceedings-article","created":{"date-parts":[[2019,4,26]],"date-time":"2019-04-26T03:49:36Z","timestamp":1556250576000},"page":"224-230","source":"Crossref","is-referenced-by-count":18,"title":["VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology"],"prefix":"10.1109","author":[{"given":"Alvin D.","family":"Wong","sequence":"first","affiliation":[]},{"given":"Kevin","family":"Su","sequence":"additional","affiliation":[]},{"given":"Hang","family":"Sun","sequence":"additional","affiliation":[]},{"given":"Arash","family":"Fayyazi","sequence":"additional","affiliation":[]},{"given":"Massoud","family":"Pedram","sequence":"additional","affiliation":[]},{"given":"Shahin","family":"Nazarian","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858353"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISEC.2017.8314213"},{"key":"ref13","first-page":"1","article-title":"If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language","author":"bromley","year":"2013","journal-title":"Proceedings of the 2013 Forum on specification and Design Languages (FDL) FDL"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194561"},{"key":"ref15","first-page":"1","article-title":"Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb\/Al-AlOx\/Nb Josephson Junctions for VLSI Circuits","volume":"25","author":"tolpygo","year":"2015","journal-title":"IEEE Trans Appl Supercond"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2018.2829776"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351603"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2018.2880343"},{"journal-title":"ATALANTA (Version 2 0","year":"1997","author":"ha","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2010.2096792"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1063\/1.114147"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2019.2892115"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2013.2244634"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/77.621942"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E98.A.2556"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/77.80745"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2017.29"},{"key":"ref9","first-page":"215","article-title":"Digital Electronics","author":"gross","year":"2016","journal-title":"Applied superconductivity Josephson effect and superconducting electronics"},{"key":"ref20","article-title":"A neutral netlist of 10 combinational circuits and a targeted translator in FORTRAN","author":"brglez","year":"1985","journal-title":"Proc 1985 IEEE Int Symp Circuits and Syst (ISCAS) Special Session on ATPG and Fault Simulation"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TASC.2017.2675889"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/54.785838"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3243470"}],"event":{"name":"2019 20th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2019,3,6]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2019,3,7]]}},"container-title":["20th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8682005\/8697223\/08697701.pdf?arnumber=8697701","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:12:30Z","timestamp":1657854750000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8697701\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/isqed.2019.8697701","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}