{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T07:19:05Z","timestamp":1725779945212},"reference-count":22,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1109\/isqed48828.2020.9136999","type":"proceedings-article","created":{"date-parts":[[2020,7,9]],"date-time":"2020-07-09T20:46:45Z","timestamp":1594327605000},"page":"243-249","source":"Crossref","is-referenced-by-count":9,"title":["A Methodology for Reusable Physical Design"],"prefix":"10.1109","author":[{"given":"Edward","family":"Wang","sequence":"first","affiliation":[]},{"given":"Colin","family":"Schmidt","sequence":"additional","affiliation":[]},{"given":"Adam","family":"Izraelevitz","sequence":"additional","affiliation":[]},{"given":"John","family":"Wright","sequence":"additional","affiliation":[]},{"given":"Borivoje","family":"Nikolic","sequence":"additional","affiliation":[]},{"given":"Elad","family":"Alon","sequence":"additional","affiliation":[]},{"given":"Jonathan","family":"Bachrach","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691100"},{"article-title":"Inversion of control","year":"2005","author":"fowler","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2018.8579326"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925994"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.11"},{"key":"ref15","first-page":"1","article-title":"A modular digital VLSI flow for high-productivity SoC design","author":"khailany","year":"0","journal-title":"Proc of the 55th Annual Design Automation Conference DAC ‘18"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2013.6683966"},{"key":"ref17","first-page":"1","article-title":"C-based rapid prototyping for digital signal processing","author":"casseau","year":"0","journal-title":"2005 13th European Signal Processing Conference"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2012.6219090"},{"key":"ref19","first-page":"192","article-title":"DSP architecture optimization in Matlab\/Simulink environment","author":"nanda","year":"0","journal-title":"2008 IEEE Symposium on VLSI Circuits"},{"journal-title":"Reference methodology retrieval system","year":"0","key":"ref4"},{"key":"ref3","article-title":"Wire Routing is NP-Complete","author":"cramer","year":"1982","journal-title":"Department of Computer Science University of Utrecht Tech Rep RUU-CS-82–4"},{"article-title":"alloy-asic - The Modular VLSI Build System","year":"0","author":"christopher","key":"ref6"},{"year":"0","key":"ref5","article-title":"OpenPiton-ZC706"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.81"},{"journal-title":"PLSI A portable VLSI flow","year":"2017","author":"dabbelt","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815968"},{"key":"ref9","first-page":"1216","author":"bachrach","year":"2012","journal-title":"Chisel Constructing Hardware in a Scala Embedded Language"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2005.12"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2001.934194"},{"journal-title":"Sponge Paint - a procedural layout library in java","year":"2000","author":"shen","key":"ref21"}],"event":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2020,3,25]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2020,3,26]]}},"container-title":["2020 21st International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9131689\/9136966\/09136999.pdf?arnumber=9136999","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:56:44Z","timestamp":1656453404000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9136999\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/isqed48828.2020.9136999","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}