{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T08:19:15Z","timestamp":1730276355543,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1109\/isqed48828.2020.9137020","type":"proceedings-article","created":{"date-parts":[[2020,7,9]],"date-time":"2020-07-09T20:46:45Z","timestamp":1594327605000},"page":"408-414","source":"Crossref","is-referenced-by-count":1,"title":["DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache"],"prefix":"10.1109","author":[{"given":"Jinbo","family":"Chen","sequence":"first","affiliation":[]},{"given":"Keren","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Xiaochen","family":"Guo","sequence":"additional","affiliation":[]},{"given":"Patrick","family":"Girard","sequence":"additional","affiliation":[]},{"given":"Yuanqing","family":"Cheng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"binkert","year":"2011","journal-title":"The gem5 Simulator SIGARCH Comput Archit News"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"ref13","first-page":"214","article-title":"A 7mb STT-RAM in 22FFL FINFET technology with 4ns read sensing time at 0.9v using write-verify-write scheme and offset-cancellation sensing technique","author":"wei","year":"0","journal-title":"IEEE Int Solid-State Circ Conf (ISSCC)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2090914"},{"journal-title":"Using Cache-coloring to Mitigate Inter-set Write Variation in Non-volatile Caches","year":"2013","author":"mittal","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2389113"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2017.8203453"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3299874.3317987"},{"key":"ref19","first-page":"1","article-title":"Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-RAM for high-performance CPU","author":"noguchi","year":"0","journal-title":"Proc Symp VLSI circuits (VLSI)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.7567\/JJAP.56.04CN02"},{"key":"ref3","first-page":"1311","article-title":"System level exploration of a STT-RAM based level 1 data-cache","author":"komalan","year":"0","journal-title":"Proceedings of Design Automation and Test in Europe Conference and Exhibition (DATE)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2533438"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/45\/29\/295002"},{"key":"ref8","first-page":"234","article-title":"i2WAP: Improving nonvolatile cache lifetime by reducing inter- and intra-set write variations","author":"wang","year":"0","journal-title":"Proc of IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2016.7574620"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228447"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"107306","DOI":"10.1360\/SSPMA2016-00185","article-title":"Recent progresses in spin transfer torque-based magnetoresistive random access memory (STT-RAM)","volume":"46","author":"zhao","year":"2016","journal-title":"Scientia Sinica Physica, Mechanica & Astronomica"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.4231\/D33R0PV04"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2557326"}],"event":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2020,3,25]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2020,3,26]]}},"container-title":["2020 21st International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9131689\/9136966\/09137020.pdf?arnumber=9137020","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:52:42Z","timestamp":1656453162000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9137020\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/isqed48828.2020.9137020","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}