{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T23:06:57Z","timestamp":1725750417970},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,4,7]]},"DOI":"10.1109\/isqed51717.2021.9424279","type":"proceedings-article","created":{"date-parts":[[2021,5,11]],"date-time":"2021-05-11T00:09:51Z","timestamp":1620691791000},"page":"482-487","source":"Crossref","is-referenced-by-count":1,"title":["Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits"],"prefix":"10.1109","author":[{"given":"Soomin","family":"Kim","sequence":"first","affiliation":[]},{"given":"Taewhan","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942064"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/196244.196283"},{"key":"ref12","article-title":"Iwls 2005 benchmarks","author":"albrecht","year":"2005","journal-title":"Tech Rep"},{"journal-title":"Logic Synthesis and Verification Algorithms","year":"2006","author":"hachtel","key":"ref13"},{"journal-title":"V12 1 User’s Manual for CPLEX","year":"2009","author":"cplex","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2373031"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090927"},{"key":"ref6","article-title":"Design and application of multimodal power gating structures","author":"ehsan","year":"2009","journal-title":"IEEE ISQED"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429448"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001354"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2293881"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329362"},{"journal-title":"Low Power Methodology Manual For System-on-Chip Design","year":"2007","author":"flynn","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203833"}],"event":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2021,4,7]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2021,4,9]]}},"container-title":["2021 22nd International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9424228\/9424248\/09424279.pdf?arnumber=9424279","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:41:22Z","timestamp":1652197282000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9424279\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,7]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/isqed51717.2021.9424279","relation":{},"subject":[],"published":{"date-parts":[[2021,4,7]]}}}