{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T22:41:25Z","timestamp":1725576085042},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,4,7]]},"DOI":"10.1109\/isqed51717.2021.9424336","type":"proceedings-article","created":{"date-parts":[[2021,5,10]],"date-time":"2021-05-10T20:09:51Z","timestamp":1620677391000},"page":"233-237","source":"Crossref","is-referenced-by-count":0,"title":["Formal Verification Aware Redundant Sequential Logic Optimization to Improve Design Utilization"],"prefix":"10.1109","author":[{"given":"Rushabh","family":"Shah","sequence":"first","affiliation":[]},{"given":"Krishna","family":"Agrawal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580074"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2001.952305"},{"key":"ref6","first-page":"2","article-title":"Logic Optimization by Output Phase Assignment in Dynamic Logic Synthesis","author":"puri","year":"1997","journal-title":"Proceedings of the 1996 IEEE\/ACM International conference on Computer-aided Design"},{"key":"ref5","first-page":"151","article-title":"Scalable Don’t-Care-Based Logic Optimization and Resynthesis","author":"robert brayton","year":"2009","journal-title":"Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays"},{"key":"ref2","article-title":"Using combinational verification for sequential circuits","author":"ranjan","year":"1999","journal-title":"Design Automation and Test in Europe Conference and Exhibition"},{"key":"ref1","article-title":"Formally Verified Redundancy Removal","author":"hendricx","year":"1999","journal-title":"Design Automation and Test in Europe Conference and Exhibition"}],"event":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2021,4,7]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2021,4,9]]}},"container-title":["2021 22nd International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9424228\/9424248\/09424336.pdf?arnumber=9424336","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T11:41:24Z","timestamp":1652182884000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9424336\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,7]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/isqed51717.2021.9424336","relation":{},"subject":[],"published":{"date-parts":[[2021,4,7]]}}}