{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T22:44:40Z","timestamp":1725576280055},"reference-count":3,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,7]],"date-time":"2021-04-07T00:00:00Z","timestamp":1617753600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,4,7]]},"DOI":"10.1109\/isqed51717.2021.9424354","type":"proceedings-article","created":{"date-parts":[[2021,5,10]],"date-time":"2021-05-10T20:09:51Z","timestamp":1620677391000},"page":"314-314","source":"Crossref","is-referenced-by-count":0,"title":["Performance Investigation of a Si\/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations"],"prefix":"10.1109","author":[{"given":"Suruchi","family":"Sharma","sequence":"first","affiliation":[]},{"given":"Rikmantra","family":"Basu","sequence":"additional","affiliation":[]},{"given":"Baljit","family":"Kaur","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref3","article-title":"Interface Trap charges associated reliability analysis of Si\/Ge heterojunction dopingless TFET","author":"sharma","year":"0","journal-title":"accepted for publication in IET Circuits Devices & Systems"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2019.0290"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nature10679"}],"event":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2021,4,7]]},"location":"Santa Clara, CA, USA","end":{"date-parts":[[2021,4,9]]}},"container-title":["2021 22nd International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9424228\/9424248\/09424354.pdf?arnumber=9424354","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T11:41:22Z","timestamp":1652182882000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9424354\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4,7]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/isqed51717.2021.9424354","relation":{},"subject":[],"published":{"date-parts":[[2021,4,7]]}}}