{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:37:34Z","timestamp":1740101854877,"version":"3.37.3"},"reference-count":45,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,4,5]],"date-time":"2023-04-05T00:00:00Z","timestamp":1680652800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,5]],"date-time":"2023-04-05T00:00:00Z","timestamp":1680652800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100009224","name":"Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100009224","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,4,5]]},"DOI":"10.1109\/isqed57927.2023.10129346","type":"proceedings-article","created":{"date-parts":[[2023,5,24]],"date-time":"2023-05-24T17:33:09Z","timestamp":1684949589000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP"],"prefix":"10.1109","author":[{"given":"Dake","family":"Chen","sequence":"first","affiliation":[{"name":"University of Southern California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuan","family":"Zhou","sequence":"additional","affiliation":[{"name":"University of Southern California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yinghua","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Southern California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuke","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Southern California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaixin","family":"Yang","sequence":"additional","affiliation":[{"name":"University of Southern California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Rittenbach","sequence":"additional","affiliation":[{"name":"USC Information Sciences Institute"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pierluigi","family":"Nuzzo","sequence":"additional","affiliation":[{"name":"University of Southern California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter A.","family":"Beerel","sequence":"additional","affiliation":[{"name":"University of Southern California"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2772817"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774603"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530542"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2021.3108487"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED48828.2020.9136991"},{"key":"ref37","article-title":"GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists","author":"alrahis","year":"2021","journal-title":"IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2915606"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2018.8607163"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643476"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3431389"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.23919\/DATE54114.2022.9774729","article-title":"JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption","author":"li","year":"2022","journal-title":"2022 Design Automation & Test in Europe Conf (DATE)"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3089555"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3060345"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3526241.3530377"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3342099"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415667"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2511144"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/HOST45689.2020.9300256"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643498"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2740364"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-66787-4_10"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415669"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942134"},{"article-title":"SAT-based key determination attack for improving the quality assessment of logic locking mechanisms","year":"0","author":"merten","key":"ref45"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST47458.2019.9006720"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC53125.2021.9606979"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715163"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.3115\/1620853.1620885"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.24963\/ijcai.2021\/610"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2019.8741028"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.193"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DFT52944.2021.9568356"},{"key":"ref43","article-title":"Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks","author":"sisejkovic","year":"2021","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3113035"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3453688.3461760"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474039"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586159"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-99524-9_1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2028166"},{"key":"ref4","first-page":"175","article-title":"CAS-lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme","author":"shakya","year":"2020","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems 2020"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317831"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/HOST49136.2021.9702267"}],"event":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2023,4,5]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2023,4,7]]}},"container-title":["2023 24th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10129281\/10129282\/10129346.pdf?arnumber=10129346","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,12]],"date-time":"2023-06-12T17:55:09Z","timestamp":1686592509000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10129346\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4,5]]},"references-count":45,"URL":"https:\/\/doi.org\/10.1109\/isqed57927.2023.10129346","relation":{},"subject":[],"published":{"date-parts":[[2023,4,5]]}}}