{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T01:37:22Z","timestamp":1725759442365},"reference-count":27,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T00:00:00Z","timestamp":1712102400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T00:00:00Z","timestamp":1712102400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,4,3]]},"DOI":"10.1109\/isqed60706.2024.10528750","type":"proceedings-article","created":{"date-parts":[[2024,5,16]],"date-time":"2024-05-16T17:21:18Z","timestamp":1715880078000},"page":"1-8","source":"Crossref","is-referenced-by-count":0,"title":["FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization"],"prefix":"10.1109","author":[{"given":"Akash","family":"Levy","sequence":"first","affiliation":[{"name":"Stanford University,Dept. of Electrical Eng.,Stanford,CA"}]},{"given":"Joe","family":"Walston","sequence":"additional","affiliation":[{"name":"AI, Distinguished Arch. Synopsys, Inc.,Sunnyvale,CA"}]},{"given":"Sourav","family":"Samanta","sequence":"additional","affiliation":[{"name":"R&D Engineer Synopsys, Inc.,Sunnyvale,CA"}]},{"given":"Priyanka","family":"Raina","sequence":"additional","affiliation":[{"name":"Stanford University,Dept. of Electrical Eng.,Stanford,CA"}]},{"given":"Stelios","family":"Diamantidis","sequence":"additional","affiliation":[{"name":"AI, Distinguished Arch. Synopsys, Inc.,Sunnyvale,CA"}]}],"member":"263","reference":[{"journal-title":"Synopsys Chip Implementation and Signoff","year":"2022","key":"ref1"},{"year":"2022","key":"ref2","article-title":"Cadence Design Tools"},{"key":"ref3","article-title":"Semi-supervised classification with graph convolutional networks","author":"Kipf","year":"2016","journal-title":"arXiv preprint arXiv:1609.02907"},{"key":"ref4","article-title":"RISC-V: high performance embedded SweRV\u2122 core microarchitecture, performance and CHIPS Alliance","author":"Marena","year":"2019","journal-title":"Western Digital Corporation"},{"volume-title":"Siemens Aprisa","year":"2022","key":"ref5"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED51717.2021.9424251"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC52403.2022.9712578"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351885"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045559"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3380446.3430622"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-03544-w"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218643"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473914"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218515"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586188"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527444"},{"key":"ref17","first-page":"1","article-title":"Accurate operation delay prediction for FPGA HLS using graph neural networks","volume-title":"Proceedings of the 39th International Conference on Computer-Aided Design","author":"Ustun"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530408"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3185540"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.24963\/ijcai.2021\/637"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23915\/distill.00033"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/72.572108"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD52597.2021.9531070"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2917698"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665689"},{"article-title":"Yosys: A free Verilog synthesis suite","volume-title":"Proceedings of the 21st Austrian Workshop on Microelectronics (Austrochip)","author":"Wolf","key":"ref26"},{"key":"ref27","article-title":"Adam: A method for stochastic optimization","author":"Kingma","year":"2014","journal-title":"arXiv preprint arXiv:1412.6980"}],"event":{"name":"2024 25th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2024,4,3]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2024,4,5]]}},"container-title":["2024 25th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10528356\/10528364\/10528750.pdf?arnumber=10528750","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,17]],"date-time":"2024-05-17T17:23:15Z","timestamp":1715966595000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10528750\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4,3]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/isqed60706.2024.10528750","relation":{},"subject":[],"published":{"date-parts":[[2024,4,3]]}}}