{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,17]],"date-time":"2025-10-17T14:29:08Z","timestamp":1760711348683},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T00:00:00Z","timestamp":1712102400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T00:00:00Z","timestamp":1712102400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,4,3]]},"DOI":"10.1109\/isqed60706.2024.10528752","type":"proceedings-article","created":{"date-parts":[[2024,5,16]],"date-time":"2024-05-16T17:21:18Z","timestamp":1715880078000},"page":"1-8","source":"Crossref","is-referenced-by-count":4,"title":["Roofline Performance Analysis of DNN Architectures on CPU and GPU Systems"],"prefix":"10.1109","author":[{"given":"H C","family":"Prashanth","sequence":"first","affiliation":[{"name":"International Institute of Information Technology Bangalore,Bangalore,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Madhav","family":"Rao","sequence":"additional","affiliation":[{"name":"IIIT-Bangalore,Bangalore,India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3154776"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3229767"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2022.3151619"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2972167"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3221473"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DSD57027.2022.00066"},{"key":"ref7","first-page":"627","article-title":"Power-efficient layer mapping for cnns on integrated cpu and gpu platforms: A case study","volume-title":"2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)","author":"Wang"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DSD57027.2022.00051"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3217226"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TMC.2023.3265111"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2777863"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/P3HPC54578.2021.00008"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/PMBS.2018.8641578"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3039278"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID51830.2021.00046"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TLA.2020.9082927"},{"key":"ref17","first-page":"1","article-title":"Neuromax: A high throughput, multithreaded, log-based accelerator for convolutional neural networks","volume-title":"2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","author":"Qureshi"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3184520"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2017.7975270"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DSD57027.2022.00051"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00048"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46079-6_24"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3458864.3467882"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICPPW.2010.38"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"}],"event":{"name":"2024 25th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2024,4,3]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2024,4,5]]}},"container-title":["2024 25th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10528356\/10528364\/10528752.pdf?arnumber=10528752","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,17]],"date-time":"2024-05-17T05:10:28Z","timestamp":1715922628000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10528752\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4,3]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/isqed60706.2024.10528752","relation":{},"subject":[],"published":{"date-parts":[[2024,4,3]]}}}