{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,13]],"date-time":"2026-01-13T22:44:32Z","timestamp":1768344272273,"version":"3.49.0"},"reference-count":30,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T00:00:00Z","timestamp":1712102400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T00:00:00Z","timestamp":1712102400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,4,3]]},"DOI":"10.1109\/isqed60706.2024.10528770","type":"proceedings-article","created":{"date-parts":[[2024,5,16]],"date-time":"2024-05-16T17:21:18Z","timestamp":1715880078000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Automated Assertion Checker Generator and Information Flow Tracking for Security Verification"],"prefix":"10.1109","author":[{"given":"Miguel Angel Alfaro","family":"Zapata","sequence":"first","affiliation":[{"name":"McGill University,Electrical and Computing Engineering,Montreal,Canada"}]},{"given":"Amirhossein","family":"Shahshahani","sequence":"additional","affiliation":[{"name":"McGill University,Electrical and Computing Engineering,Montreal,Canada"}]},{"given":"Zeljko","family":"Zilic","sequence":"additional","affiliation":[{"name":"McGill University,Electrical and Computing Engineering,Montreal,Canada"}]}],"member":"263","reference":[{"key":"ref1","article-title":"Wilson research group fpga functional verification trends","author":"Foster","year":"2022","journal-title":"White Paper. Wilson Research Group and Mentor, A Siemens Business"},{"key":"ref2","article-title":"System-on-chip security assertions","author":"Lyu","year":"2020","journal-title":"arXiv preprint arXiv:2001.06719"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-013-5403-y"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287660"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3565801"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-49025-0"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3447867"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927266"},{"key":"ref9","volume-title":"Verification and Synthesis of Information Flow Secure Hardware Designs","author":"Ardeshiricham","year":"2020"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2775054.2694372"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2017.8242062"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-017-0001-6"},{"key":"ref13","volume-title":"Open cores","year":"2021"},{"key":"ref14","volume-title":"Vexriscv","year":"2022"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837337"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541947"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508258"},{"key":"ref18","volume-title":"Yosys open synthesis suite","author":"Wolf","year":"2016"},{"key":"ref19","first-page":"2549","article-title":"{CellIFT}: Leveraging cells for scalable and precise dynamic information flow tracking in {RTL}","volume-title":"31st USENIX Security Symposium (USENIX Security 22)","author":"Solt"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/360051.360056"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062206"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193920"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484908"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED54688.2022.9806292"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3510578"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8586-4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-16214-0_42"},{"key":"ref28","volume-title":"Pyverilog","year":"2022"},{"key":"ref29","volume-title":"Yosys: Yosys open synthesis suite","year":"2023"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657085"}],"event":{"name":"2024 25th International Symposium on Quality Electronic Design (ISQED)","location":"San Francisco, CA, USA","start":{"date-parts":[[2024,4,3]]},"end":{"date-parts":[[2024,4,5]]}},"container-title":["2024 25th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10528356\/10528364\/10528770.pdf?arnumber=10528770","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,5,17]],"date-time":"2024-05-17T05:09:01Z","timestamp":1715922541000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10528770\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4,3]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/isqed60706.2024.10528770","relation":{},"subject":[],"published":{"date-parts":[[2024,4,3]]}}}