{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T04:08:15Z","timestamp":1748750895682,"version":"3.41.0"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,4,23]],"date-time":"2025-04-23T00:00:00Z","timestamp":1745366400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,23]],"date-time":"2025-04-23T00:00:00Z","timestamp":1745366400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,4,23]]},"DOI":"10.1109\/isqed65160.2025.11014405","type":"proceedings-article","created":{"date-parts":[[2025,5,30]],"date-time":"2025-05-30T17:43:30Z","timestamp":1748627010000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["RL-Driven Fine-Grained Power Gating for Modern Processors Using Multi-Layer Perceptron Models"],"prefix":"10.1109","author":[{"given":"Naman","family":"Kalra","sequence":"first","affiliation":[{"name":"Indian Institute of Technology,Dept. of Electrical Engineering,Tirupati,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaynarayan T","family":"Tudu","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology,Dept. of Computer Science Engineering,Tirupati,India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45937-5_19"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/iccad.2008.4681569"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653652"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013249"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/isqed.2006.102"},{"key":"ref6","first-page":"345","article-title":"Compiler-directed fine grain power gating for leakage power reduction in microprocessor functional units","author":"Komoda","year":"2013","journal-title":"ISLPED\u201913"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.836315"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645830"}],"event":{"name":"2025 26th International Symposium on Quality Electronic Design (ISQED)","start":{"date-parts":[[2025,4,23]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2025,4,25]]}},"container-title":["2025 26th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11014297\/11014302\/11014405.pdf?arnumber=11014405","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,31]],"date-time":"2025-05-31T04:43:49Z","timestamp":1748666629000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11014405\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4,23]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/isqed65160.2025.11014405","relation":{},"subject":[],"published":{"date-parts":[[2025,4,23]]}}}