{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,14]],"date-time":"2026-07-14T12:21:30Z","timestamp":1784031690725,"version":"3.55.0"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T00:00:00Z","timestamp":1775606400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T00:00:00Z","timestamp":1775606400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,8]]},"DOI":"10.1109\/isqed69900.2026.11534654","type":"proceedings-article","created":{"date-parts":[[2026,5,28]],"date-time":"2026-05-28T22:26:58Z","timestamp":1780007218000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["A Low-overhead Dilithium-NTT Architecture using Accelerated K-RED Modular Reduction Unit"],"prefix":"10.1109","author":[{"given":"Harsh","family":"Gupta","sequence":"first","affiliation":[{"name":"Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Aryan","family":"Goyal","sequence":"additional","affiliation":[{"name":"Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paranjay","family":"Dhadwal","sequence":"additional","affiliation":[{"name":"Birla Institute of Technology and Science (BITS) Pilani-Goa Campus,India,403726"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jugal","family":"Gandhi","sequence":"additional","affiliation":[{"name":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Diksha","family":"Shekhawat","sequence":"additional","affiliation":[{"name":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Santosh","sequence":"additional","affiliation":[{"name":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jai Gopal","family":"Pandey","sequence":"additional","affiliation":[{"name":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-39799-x_31"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/359340.359342"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1137\/S0036144598347011"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/237814.237866"},{"key":"ref5","article-title":"Submission Requirements and Evaluation Criteria for the Post-quantum Cryptography Standardization Process","year":"2016"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2018.i1.238-268"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.6028\/nist.fips.204"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-48965-0_8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-47721-7_24"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.2307\/2007970"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH51176.2021.00028"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2021.3073475"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS56072.2025.11043587"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401170"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2025.3576934"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00070"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3316393"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID60093.2024.00082"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3304416"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT52863.2021.9609917"},{"key":"ref21","first-page":"91","article-title":"Efficient Access Scheme for Multi-bank based NTT Architecture through Conflict Graph","volume-title":"Proceedings of the 59th ACM\/IEEE Design Automation Conference, DAC \u201922","author":"Chen"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS46773.2023.10181340"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS56072.2025.11044053"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2022.3144101"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3179459"}],"event":{"name":"2026 27th International Symposium on Quality Electronic Design (ISQED)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,4,8]]},"end":{"date-parts":[[2026,4,10]]}},"container-title":["2026 27th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11534651\/11534652\/11534654.pdf?arnumber=11534654","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T04:24:23Z","timestamp":1780028663000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11534654\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,8]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/isqed69900.2026.11534654","relation":{},"subject":[],"published":{"date-parts":[[2026,4,8]]}}}