{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T05:04:02Z","timestamp":1780031042937,"version":"3.53.1"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T00:00:00Z","timestamp":1775606400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T00:00:00Z","timestamp":1775606400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,8]]},"DOI":"10.1109\/isqed69900.2026.11534664","type":"proceedings-article","created":{"date-parts":[[2026,5,28]],"date-time":"2026-05-28T22:26:58Z","timestamp":1780007218000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Reverse Engineering RTL Models from DSP Slices in FPGA Netlists"],"prefix":"10.1109","author":[{"given":"Avinash Hegde","family":"Kota","sequence":"first","affiliation":[{"name":"University of Cincinnati,Digital Design Environments Lab,ECE Department,Cincinnati,Ohio,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Aparajithan Nathamuni","family":"Venkatesan","sequence":"additional","affiliation":[{"name":"University of Cincinnati,Digital Design Environments Lab,ECE Department,Cincinnati,Ohio,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ranga","family":"Vemuri","sequence":"additional","affiliation":[{"name":"University of Cincinnati,Digital Design Environments Lab,ECE Department,Cincinnati,Ohio,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John","family":"Emmert","sequence":"additional","affiliation":[{"name":"University of Cincinnati,Digital Design Environments Lab,ECE Department,Cincinnati,Ohio,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IVSW.2017.8031550"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-021-00268-5"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2331672"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339165"},{"key":"ref5","volume-title":"Project X-Ray"},{"key":"ref6","volume-title":"The reference community for Free and Open Source gateware IP cores"},{"key":"ref7","volume-title":"Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3310273.3323419"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.1109\/ISQED57927.2023.10129373","article-title":"Reverse Engineering Word-Level Models from Look-Up Table Netlists","author":"Narayanan","year":"2023"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID57277.2023.00083"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/isvlsi59464.2023.10238540"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/mwscas57524.2023.10406081"},{"key":"ref13","volume-title":"7series FPGAs DSP48E1 User Guide (UG479)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/fpl.2012.6339163"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/fpl.2016.7577373"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/isqed.2019.8697444"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1137\/0201010"},{"key":"ref18","volume-title":"Vivado Design Suite User Guide: Synthesis (UG901)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/fpl.2012.6339165"}],"event":{"name":"2026 27th International Symposium on Quality Electronic Design (ISQED)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,4,8]]},"end":{"date-parts":[[2026,4,10]]}},"container-title":["2026 27th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11534651\/11534652\/11534664.pdf?arnumber=11534664","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T04:24:30Z","timestamp":1780028670000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11534664\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,8]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/isqed69900.2026.11534664","relation":{},"subject":[],"published":{"date-parts":[[2026,4,8]]}}}