{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T05:04:07Z","timestamp":1780031047401,"version":"3.53.1"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T00:00:00Z","timestamp":1775606400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T00:00:00Z","timestamp":1775606400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,8]]},"DOI":"10.1109\/isqed69900.2026.11534779","type":"proceedings-article","created":{"date-parts":[[2026,5,28]],"date-time":"2026-05-28T22:26:58Z","timestamp":1780007218000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Agentic AI for Chip Design Verification: Failure Modes, Metrics, and Coverage Closure"],"prefix":"10.1109","author":[{"given":"Noah","family":"Marosok","sequence":"first","affiliation":[{"name":"University of California San Diego,Department of Electrical and Computer Engineering,La Jolla,CA,92093"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marcus","family":"Halm","sequence":"additional","affiliation":[{"name":"University of California Davis,Department of Electrical and Computer Engineering,Davis,CA,95616"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kevin Immanuel","family":"Gubbi","sequence":"additional","affiliation":[{"name":"University of California Davis,Department of Electrical and Computer Engineering,Davis,CA,95616"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohammadnavid","family":"Tarighat","sequence":"additional","affiliation":[{"name":"University of California Davis,Department of Electrical and Computer Engineering,Davis,CA,95616"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Neusha","family":"Javidnia","sequence":"additional","affiliation":[{"name":"University of California San Diego,Department of Electrical and Computer Engineering,La Jolla,CA,92093"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Soheil","family":"Zibakhsh-Shabgahi","sequence":"additional","affiliation":[{"name":"University of California San Diego,Department of Electrical and Computer Engineering,La Jolla,CA,92093"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ke","family":"Huang","sequence":"additional","affiliation":[{"name":"San Diego State University,Department of Electrical and Computer Engineering,San Diego,CA,92182"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Setareh","family":"Rafatirad","sequence":"additional","affiliation":[{"name":"University of California Davis,Department of Electrical and Computer Engineering,Davis,CA,95616"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hossein","family":"Sayadi","sequence":"additional","affiliation":[{"name":"California State University,Department of Computer Engineering and Computer Science,Long Beach,CA,90840"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Farinaz","family":"Koushanfar","sequence":"additional","affiliation":[{"name":"University of California San Diego,Department of Electrical and Computer Engineering,La Jolla,CA,92093"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[{"name":"University of California Davis,Department of Electrical and Computer Engineering,Davis,CA,95616"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","article-title":"Scaling laws for neural language models","volume":"abs\/2001.08361","author":"Kaplan","year":"2020","journal-title":"CoRR"},{"key":"ref2","article-title":"Training compute-optimal large language models","author":"Hoffmann","year":"2022"},{"key":"ref3","article-title":"2024 wilson research group ic\/asic functional verification trend report","author":"Foster","year":"2025"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICLAD65226.2025.00020"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI66862.2025.11218681"},{"key":"ref6","article-title":"Architect in the loop agentic hardware design and verification","author":"Mohammed","year":"2025"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3177540.3177554"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICSE-SEIP58684.2023.00037"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD65511.2025.11189220"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/dac63849.2025.11435108"},{"key":"ref11","article-title":"All artificial, less intelligence: Genai through the lens of formal verification","author":"Gadde","year":"2024"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.2026.3657432"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3589334.3645376"},{"key":"ref14","article-title":"Protocolllm: Rtl benchmark for systemverilog generation of communication protocols","author":"Sheth","year":"2025"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1162\/tacl_a_00638"},{"key":"ref16","article-title":"React: Synergizing reasoning and acting in language models","author":"Yao","year":"2023"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/iccad57390.2023.10323812"},{"key":"ref18","article-title":"Chipnemo: Domain-adapted llms for chip design","author":"Liu","year":"2024"},{"key":"ref19","article-title":"Autochip: Automating hdl generation using llm feedback","author":"Thakur","year":"2024"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3383347"},{"key":"ref21","article-title":"Comprehensive verilog design problems: A next-generation benchmark dataset for evaluating large language models and agents on rtl design and verification","author":"Pinckney","year":"2025"},{"key":"ref22","article-title":"Spec2assertion: Automatic pre-rtl assertion generation using large language models with progressive regularization","author":"Wu","year":"2025"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691792"}],"event":{"name":"2026 27th International Symposium on Quality Electronic Design (ISQED)","location":"San Francisco, CA, USA","start":{"date-parts":[[2026,4,8]]},"end":{"date-parts":[[2026,4,10]]}},"container-title":["2026 27th International Symposium on Quality Electronic Design (ISQED)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11534651\/11534652\/11534779.pdf?arnumber=11534779","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T04:26:25Z","timestamp":1780028785000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11534779\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,8]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/isqed69900.2026.11534779","relation":{},"subject":[],"published":{"date-parts":[[2026,4,8]]}}}