{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T18:30:43Z","timestamp":1776277843163,"version":"3.50.1"},"reference-count":3,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/isscc.2006.1696062","type":"proceedings-article","created":{"date-parts":[[2006,9,22]],"date-time":"2006-09-22T17:01:13Z","timestamp":1158944473000},"page":"315-324","source":"Crossref","is-referenced-by-count":42,"title":["A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache"],"prefix":"10.1109","author":[{"given":"S.","family":"Rusu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Tam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Muljono","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Ayers","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2003.1221148"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346592"},{"key":"ref1","first-page":"657","article-title":"A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and $0.57\\mu {\\rm m}^2$ SRAM Cell","author":"bai","year":"2004","journal-title":"IEDM Technical Digest"}],"event":{"name":"2006 IEEE International Solid State Circuits Conference","location":"San Francisco, CA, USA","start":{"date-parts":[[2006,2,6]]},"end":{"date-parts":[[2006,2,9]]}},"container-title":["2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/11149\/35738\/01696062.pdf?arnumber=1696062","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,27]],"date-time":"2021-05-27T00:26:37Z","timestamp":1622075197000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1696062\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/isscc.2006.1696062","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}