{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T03:16:14Z","timestamp":1725506174229},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/isscc.2006.1696066","type":"proceedings-article","created":{"date-parts":[[2006,9,22]],"date-time":"2006-09-22T13:01:13Z","timestamp":1158930073000},"page":"353-365","source":"Crossref","is-referenced-by-count":5,"title":["A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core"],"prefix":"10.1109","author":[{"given":"S.","family":"Wijeratne","sequence":"first","affiliation":[]},{"given":"N.","family":"Siddaiah","sequence":"additional","affiliation":[]},{"given":"S.","family":"Mathew","sequence":"additional","affiliation":[]},{"given":"M.","family":"Anders","sequence":"additional","affiliation":[]},{"given":"R.","family":"Krishnamurthy","sequence":"additional","affiliation":[]},{"given":"J.","family":"Anderson","sequence":"additional","affiliation":[]},{"family":"Seung Hwang","sequence":"additional","affiliation":[]},{"given":"M.","family":"Ernest","sequence":"additional","affiliation":[]},{"given":"M.","family":"Nardin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332594"},{"key":"ref3","first-page":"657","article-title":"A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and $0.57\\mu {\\rm m^2}$ SRAM Cell","author":"bai","year":"2004","journal-title":"IEDM Technical Digest"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810056"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332640"},{"key":"ref1","first-page":"324","article-title":"A $0.18\\mu {\\rm m}$ CMOS IA32 Microprocessor with a 4GHz Integer Execution Unit","author":"sager","year":"0","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2006 IEEE International Solid State Circuits Conference","start":{"date-parts":[[2006,2,6]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2006,2,9]]}},"container-title":["2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/11149\/35738\/01696066.pdf?arnumber=1696066","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,26]],"date-time":"2021-05-26T20:26:49Z","timestamp":1622060809000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1696066\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/isscc.2006.1696066","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}