{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:57:02Z","timestamp":1725494222062},"reference-count":1,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1109\/isscc.2006.1696201","type":"proceedings-article","created":{"date-parts":[[2006,9,22]],"date-time":"2006-09-22T17:01:13Z","timestamp":1158944473000},"page":"1502-1511","source":"Crossref","is-referenced-by-count":3,"title":["Free-Running Ring Frequency Synthesizer"],"prefix":"10.1109","author":[{"given":"D.J.","family":"Allen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.L.","family":"Carley","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"420","article-title":"A Self-Biased PLL With Current-Mode Filter for Clock Generation","author":"yan","year":"0","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2006 IEEE International Solid State Circuits Conference","start":{"date-parts":[[2006,2,6]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2006,2,9]]}},"container-title":["2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/11149\/35738\/01696201.pdf?arnumber=1696201","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,27]],"date-time":"2021-05-27T00:27:44Z","timestamp":1622075264000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1696201\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"references-count":1,"URL":"https:\/\/doi.org\/10.1109\/isscc.2006.1696201","relation":{},"subject":[],"published":{"date-parts":[[2006]]}}}