{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,30]],"date-time":"2025-09-30T10:40:07Z","timestamp":1759228807053},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,2]]},"DOI":"10.1109\/isscc.2008.4523281","type":"proceedings-article","created":{"date-parts":[[2008,5,21]],"date-time":"2008-05-21T11:39:02Z","timestamp":1211369942000},"page":"510-632","source":"Crossref","is-referenced-by-count":25,"title":["A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure"],"prefix":"10.1109","author":[{"given":"Ki-Tae","family":"Park","sequence":"first","affiliation":[]},{"given":"Doogon","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Soonwook","family":"Hwang","sequence":"additional","affiliation":[]},{"given":"Myounggon","family":"Kang","sequence":"additional","affiliation":[]},{"given":"Hoosung","family":"Cho","sequence":"additional","affiliation":[]},{"given":"Youngwook","family":"Jeong","sequence":"additional","affiliation":[]},{"given":"Yong-Il","family":"Seo","sequence":"additional","affiliation":[]},{"given":"Jaehoon","family":"Jang","sequence":"additional","affiliation":[]},{"given":"Han-Soo","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Soon-Moon","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Yeong-Taek","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Changhyun","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Won-Seong","family":"Lee","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234303"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2000.904284"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884079"},{"key":"7","first-page":"298","article-title":"scalable wordline shielding scheme using dummy cell beyond 40nm nand flash memory for eliminating abnormal disturb of edge memory cell","author":"park","year":"2006","journal-title":"Ext Abst of SSDM"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339708"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346902"},{"key":"4","first-page":"265","article-title":"highly area efficient and cost effective double stacked s3 (stacked single-crystal si) peripheral cmos sstft and sram cell technlogy for 512mbit density sram","author":"jung","year":"2004","journal-title":"IEDM Dig Tech Papers"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342709"},{"key":"8","first-page":"128","article-title":"a3.3v 32mb nand flash memory with incremental step pulse programming scheme","author":"suh","year":"1995","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2008 IEEE International Solid-State Circuits Conference","start":{"date-parts":[[2008,2,3]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2008,2,7]]}},"container-title":["2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4497158\/4523032\/04523281.pdf?arnumber=4523281","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,4]],"date-time":"2021-06-04T12:51:13Z","timestamp":1622811073000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4523281\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,2]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/isscc.2008.4523281","relation":{},"subject":[],"published":{"date-parts":[[2008,2]]}}}